Question Zen 6 Speculation Thread

[MS_AT]

Pretty much everything relevant that does SIMD supports AVX512 since that is what's on server for either vendor.

Sorry I wasn't clear. I was speaking from client point of view where Apple can push SME usage via system libraries or their own apps, something Intel or AMD are unable to do on Windows with AVX512.

 

[Timmah!]

You'll get 15% and you're gonna like it.

We will, if it comes with additional 8 cores (16 to 24) under 1000.

 

[HurleyBird]

For Medusa Point it's going from 4-core CCX with 16MB L3 to 12-core CCX with 48MB L3. The performance jump will be much higher than in desktop.

EDIT: Totally misread what you wrote, somehow. Still, will keep this up since there's some fun speculation in it.

How sure are you that it's a 4-core CCX, rather than you know there are 4 LP cores, which you then infer a 4-core CCX from?

Because the intersection of your 4-core 16MB CCX leak, and the MLID Medusa Point die diagram leak just makes everything really confusing. For reference:


(supposedly ~200mm2 for the IOD)

That structure on the IOD that looks strikingly like an 8-core CCX, which is in basically where you would expect a CCX to be if you horizontally mirrored Strix? Yeah.... MLID speculates those are actually 8 WGPs which feels... off. Maybe he knows something because I don't think there's anyway to see that without thinking "CCX."

And the L3 on this CCX-looking structure? Pretty much the exact size you would expect for 16MB, which you've corroborated.

But assuming this is a CCX there are appear to be 8 cores, not the 4 that you claim.

But the top row of "cores" is measurably smaller than the bottom row.

So perhaps it's 4+4, with 4 LP cores and 4 full fat (or regular dense) cores?

16MB of L3 sounds like a lot for a 4-core "LP island," although the diagram suggests the L3 might be shared with the GPU... but then the diagram does not suggest a 4-core CCX.

Given MLID's hit rate on these high level diagram leaks (MI300, etc), there's a very high chance the image has some basis in reality, even if his analysis seems strange.

So we basically have a situation here where MLID posts a diagram with a structure that screams 8-core 16MB CCX IOD, but then he speculates about that being the GPU... you corroborate 16MB L3 but claim the CCX is just 4-core. The sum of all this is... pretty awkward.

 

[LightningZ71]

It is mathematically unlikely that 24C Medusa Ridge will match or even be close to that 48C monster from Intel in manufacturing cost, power consumption at competitive clocks and (r)etail price, too.

And AMD will probably still win in a lot of workloads.


They'd certainly all be on the same ring one way or another, but there's a serious factor speaking in favor of an all-Zen6 CCD:

The CCD's layout.

If Zen4c and Zen5c are anything to go by, the c variants are compressed along both axes.
In APUs, where the CPU cores only make up like 15-25% of the area, or c-only CCDs, you can fully leverage that.
But in a CCD with big cores, no matter where you place the c cores, you'd lose the gains along one of the axes, as the CCD dimensions will be determined by the big cores along at least one axis. In other words, mixing Zen6 and Zen6c in a CCD would result in roughly 50% of the c area gains getting lost to unused whitespace.
In that case, might as well go with full Zen6 cores only and just aim for higher MT perf so you can ask somewhat higher prices to make up for the slightly bigger CCD size.

Take a look at Strix Point. It appears that the C cores are only compressed along their length and not their width. In other words, the C cores are just as wide as the P cores, but the P cores are much longer. With the same strategy, it would be trivially easy for AMD to make the CCDs 6+6 with the P cores on one side and the E cores on the other. It would likely look off-centered.

The other possibility is to decide to compress the C cores on width, and have 4 P cores on one side and 8 C cores on the other.

 

[Geddagod]

You'll get 15% and you're gonna like it.

Would be pleasantly surprised if it's that high.

Increasing IPC is trivial. Doing that while maintaining IPC/CAC delta is, well.

Zen 5 fell off

 

[adroc_thurston]

Zen 5 fell off

Sure didn't.

Would be pleasantly surprised if it's that high.

That's normal.

 

[Geddagod]

Sure didn't.

Zen 5 got to be the lowest perf/watt uplift (esp at the low end of the curve) since like forever. Same perf/watt at the lower end of the curve while also moving from N5 to N4P is Intel tier work ngl.

That's normal.

Zen 2 and Zen 4 were similar IPC uplifts ig.
I fully expect a decent chunk of it to come from uncore changes tho more than just the core changes themselves.

 

[adroc_thurston]

Zen 5 got to be the lowest perf/watt uplift (esp at the low end of the curve) since like forever

No? Zen3 had like none.
Socket-level ISO power Milan had very little in raw oomph added. But hey, it fixed like every Zen glass jaw imaginable.

Same perf/watt at the lower end of the curve while also moving from N5 to N4P is Intel tier work ngl.

?

I fully expect a decent chunk of it to come from uncore changes tho more than just the core changes themselves.

that's focused on power than anything perf.

 

[inquiss]

No? Zen3 had like none
Socket-level ISO power Milan had very little in raw oomph added. But hey, it fixed like every Zen glass jaw imaginable.

?

that's focused on power than anything perf.

Nothing in the uncore that can help e.g. lower latency?

 

[adroc_thurston]

Nothing in the uncore that can help e.g. lower latency?

A few ns lower if you're lucky but that's about it.
It'll be higher bandwidth (probably) and certainly lower power.

 

[Kepler_L2]

EDIT: Totally misread what you wrote, somehow. Still, will keep this up since there's some fun speculation in it.

How sure are you that it's a 4-core CCX, rather than you know there are 4 LP cores, which you then infer a 4-core CCX from?

Because the intersection of your 4-core 16MB CCX leak, and the MLID Medusa Point die diagram leak just makes everything really confusing. For reference:

View attachment 117367
(supposedly ~200mm2 for the IOD)

That structure on the IOD that looks strikingly like an 8-core CCX, which is in basically where you would expect a CCX to be if you horizontally mirrored Strix? Yeah.... MLID speculates those are actually 8 WGPs which feels... off. Maybe he knows something because I don't think there's anyway to see that without thinking "CCX."

And the L3 on this CCX-looking structure? Pretty much the exact size you would expect for 16MB, which you've corroborated.

But assuming this is a CCX there are appear to be 8 cores, not the 4 that you claim.

But the top row of "cores" is measurably smaller than the bottom row.

So perhaps it's 4+4, with 4 LP cores and 4 full fat (or regular dense) cores?

16MB of L3 sounds like a lot for a 4-core "LP island," although the diagram suggests the L3 might be shared with the GPU... but then the diagram does not suggest a 4-core CCX.

Given MLID's hit rate on these high level diagram leaks (MI300, etc), there's a very high chance the image has some basis in reality, even if his analysis seems strange.

So we basically have a situation here where MLID posts a diagram with a structure that screams 8-core 16MB CCX IOD, but then he speculates about that being the GPU... you corroborate 16MB L3 but claim the CCX is just 4-core. The sum of all this is... pretty awkward.

I don't know why whoever made this diagram did 2 different sizes for the WGPs but that is definitely not an additional 8 Zen6 on the IOD.

 

[Geddagod]

No? Zen3 had like none.

AMD glazed the hell out of Zen 3 perf/watt gain

To be fair tho I never saw a ST curve for Zen 3 vs Zen 2.
This is the Zen 5 ST curve I saw from Huang:

Perhaps the ST perf/watt curve for Zen 3 vs Zen 2 would be similar, idk.

?

Zen 3 brought, at least a similar, amount of perf/watt uplift as Zen 5, while staying on the same node, while Zen 5 got the node bump of going from N4P to N5.

that's focused on power than anything perf.

That's lowkey disappointing.

I don't know why whoever made this diagram did 2 different sizes for the WGPs but that is definitely not an additional 8 Zen6 on the IOD.
View attachment 117382

T-T

 

[adroc_thurston]

AMD glazed the hell out of Zen 3 perf/watt gain

Didn't show up in Milan.

Zen 3 brought, at least a similar, amount of perf/watt uplift as Zen 5, while staying on the same node, while Zen 5 got the node bump of going from N4P to N5.

That's not a node bump.

To be fair tho I never saw a ST curve for Zen 3 vs Zen 2.

Don't even have to.

That's lowkey disappointing.

?
That's good, power is all that matters in client.

 

[DisEnchantment]

Zen 4 official spec says 71mm2 for CCD.

https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-7-7700x.html

Zen 5 is apparently 70.6 mm2

Zen 4 CCD is 66mm2, from ISSCC. 71mm2 is package size not die size.


Zen 5 CCD is smaller than Z4 CCD, by half mm2

75mm2 Zen 6 CCD die size is huge, with package probably close to 80mm2. To be seen, if remotely true, that too on N2?

For Medusa Point it's going from 4-core CCX with 16MB L3 to 12-core CCX with 48MB L3. The performance jump will be much higher than in desktop.

That's 3x more directory entries to scan, and 3x more clients to contend with in the ring. 4C/16M config is same L3 slice as DT 8C/32M. Doubtful the gains would be that different at same clock. Mobile is rather hobbled by the slower IF and the halved L/S BW.

If they can increase the private L2 with same number of access cycles, like they did for Z5 L1d would be better in my opinion rather than increasing the already huge L3 by another 50%.
Considering the stalls for apps with small memory footprint is mostly in L1 and L2. For big code footprint, they need to go to memory/V cache anyway and the bigger L3 would not help across the board (besides games) in ST especially with more cores in the ring.

But if they can get more comparators to work each cycle for tag checks while keeping same reasonable power for L2/L3 and same access latency so if they use that power budget for this then perhaps.

Zen5 has some peculiarities with higher MPKI in many workloads even considering the bigger L1d and higher L/S BW.

 

[adroc_thurston]

That's 3x more directory entries to scan, and 3x more clients to contend with in the ring

it's not a ring. it's a mesh.

If they can increase the private L2 with same number of access cycles, like they did for Z5 L1d would be better in my opinion rather than increasing the already huge L3 by another 50%.

L2 stays the same.

 

[jpiniero]

75mm2 Zen 6 CCD die size is huge, with package probably close to 80mm2. To be seen, if remotely true, that too on N2?

Well, if it ends up being waaaay to expensive to get OEM interest... there's always Hawk Tua.

 

[Geddagod]

Didn't show up in Milan.

Could it be related to the IO die changes as well?
AMD claims a 10% perf/watt uplift, but yea I agree I don't really see it Anandtech's Milan review.

That's not a node bump.

The perf/watt improvement is pretty close to a node bump. +11% perf/watt and a slight density increase from the node, and yet Zen 5 is only just as good as Zen 4 at lower power?

?
That's good, power is all that matters in client.

Muh gaming.

 

[adroc_thurston]

Could it be related to the IO die changes as well?

Milan brought very little.

The perf/watt improvement is pretty close to a node bump. +11%

That's in vacuum.

Muh gaming.

They get the v$ pile.

 

[HurleyBird]

I don't know why whoever made this diagram did 2 different sizes for the WGPs but that is definitely not an additional 8 Zen6 on the IOD.
View attachment 117382

That's one chunky GPU if it's ~200m2 3nm and the structures are even close to accurate.

8+MB of L2 on the IGPU is... interesting to say the least.

But now that I think about it, the NPU is definitely not going to be that close to the perimeter and there isn't any room to move it without changing its orientation or its dimensions or the GPU's. That's a problem.

 

[reaperrr3]

That's one chunky GPU if it's ~200m2 3nm and the structures are even close to accurate.

They most likely aren't.

These are just mock-ups, though allegedly based on actual info about chip dimensions and specs MLID received (he clearly mentioned this, btw).
That doesn't guarantee that the layout and dimensions of the GPU and NPU portions inside the IOD are all that accurate.

 

[mostwanted002]

Might be a bit early here.
Running a Zen3 system in full hopium to finally upgrade with Zen6. I know it might be too much to ask for, but is there a post/thread that can TL;DR the discussion so far??

 

[adroc_thurston]

TL;DR the discussion so far??

You get more stuff.

 

[GTracing]

Might be a bit early here.
Running a Zen3 system in full hopium to finally upgrade with Zen6. I know it might be too much to ask for, but is there a post/thread that can TL;DR the discussion so far??

Zen6 is rumored to switch to a 12 core CCX. Desktop CPUs would have up to 24 cores.

Zen6 is rumored to merge desktop and mobile. So the mainstream/high-end laptop chips would use chiplets and share a CCD with desktop. Desktop might get the bigger iGPU and NPU from mobile, or there could be different IO dies for desktop and mobile.

Some people here say it's late 2026 or 2027 and will use N2.

It's all but confirmed to use AM5.

It's rumored to get RDNA5 graphics.

 

[branch_suggestion]

New MLID claim just dropped.

 

[CakeMonster]

Has he made those other predictions before, so that magically AMD 'changed the design'? Wouldn't be the first time from someone with that kind of history.