Add to that list "V-cache slice that is bonded laterally across 2 CCDs, connecting them like a bridge"
Add to that list "V-cache slice that is bonded laterally across 2 CCDs, connecting them like a bridge"More cores are boring.
What is NOT boring?
- V-Cache
- bigger V-Cache
- V-Cache running at full speed, no clock regression
- 16 core CCD with double L3, double V-Cache.
That's not how AMD cache coherency works.Add to that list "V-cache slice that is bonded laterally across 2 CCDs, connecting them like a bridge"
Add to that list "V-cache slice that is bonded laterally across 2 CCDs, connecting them like a bridge"
SMT can be replaced with a monster OoOE, which can give the same core utilisation benefits, but for a ST.
Oh man, that was a very ambitious design. Can't help lusting at the slides here: https://www.servethehome.com/marvel...s-in-2020/marvell-thunderx3-smt4-improvement/Marvell claimed +28-121% higher throughput with +5% area from their 4-way SMT implementation. You are not going to get anywhere close to that with a few larger structures here and there.
The only latency overhead would be when one CCD needs to get data from the core of another CCD. For two CCDs, there would be a V-cache die over each CCD, plus a V-cache "bridge" die containing data that is most frequently shared between the two CCDs. It might be more expensive and have slightly higher latency but it would still beat going out to the IOD for data. The only reason AMD isn't doing something like this is coz they don't have any competition in this space so why should they bother increasing their costs?But developing algorithm to utilize it, between 2 CCDs, without latency-cost prohibitive overhead probably makes it impossible to implement.
Oh man, that was a very ambitious design. Can't help lusting at the slides here: https://www.servethehome.com/marvel...s-in-2020/marvell-thunderx3-smt4-improvement/
Must've been shortsighted executives to not use that IP for entering the laptop market.
Hmm. LPDDR6 will certainly be in market by the time Zen6 rolls out. The question is whether Zen6 will support LPDDR6.
Marvell claimed +28-121% higher throughput with +5% area from their 4-way SMT implementation. You are not going to get anywhere close to that with a few larger structures here and there.
With few cores memory latency capped workloads saw big gains from SMT. But todays 100-core systems not so much - those memory latency bound use cases will also saturate memory system without SMT . If those Intel numbers for area and performance/power handicaps are really so big only sane thing for them is to drop SMT from their server-grade cpu implementations too.
It's already changed. If those Intel numbers are right they did great mistake keeping SMT onboard so long. There's only one reason to make big power inefficient cores - to go after best possible thread performance. Splitting that performance to half or 1/4 with SMT is just plain stupidity. For workloads that do not need best possible thread performance use power-optimized cores instead of SMT neutered power hog big cores. Those power-optimized little cores might benefit from smt in some niche cases though.ThunderX3 was 60 cores and still got large gains.
"Hardware multithreading makes stuff go faster" isn't that controversial of a statement. It applies from the niche (hundreds of single-issue cores with 16 threads each, running a large SMP Linux instance) to the normal (large server chips from mainstream vendors.)
It makes heterogeneity harder, and having smaller more efficient cores on the same die arguably makes it less necessary, but SMT exists for good reason, sees real gains, and that isn't going to change.
It's already changed. If those Intel numbers are right they did great mistake keeping SMT onboard so long. There's only one reason to make big power inefficient cores - to go after best possible thread performance. Splitting that performance to half or 1/4 with SMT is just plain stupidity. For workloads that do not need best possible thread performance use power-optimized cores instead of SMT neutered power hog big cores. Those power-optimized little cores might benefit from smt in some niche cases though.
"Using smaller cores is better than doing SMT on bigger cores" inevitably leads to "okay, what if we add hardware MT to smaller cores?" - and I can attest from experience that that is something that does, in fact, happen; the manycore Linux I mentioned before wasn't hypothetical.
The core argument, or a core argument, of SMT is that you have a given target for size and complexity of a core and you also want a cheap throughput win on the side. I struggle to think of a category of core where that ceases to be applicable.
Funny that Intel is blaming SMT when their rival is eclipsing their ST performance with SMT enabledWhat Intel basically said is that they are losing about one generation of ST performance by implementing SMT. And it's clear that they can't afford it anymore as there is rivals that goes all in for ST performance.
Funny that Intel is blaming SMT when their rival is eclipsing their ST performance with SMT enabled
Additionally, newer versions of the Linux kernel than the version in SUSE Linux Enterprise Server SP1 contain enhancements that enhance SMT behavior for POWER7 processors. These enhancements migrate work from tertiary threads to secondary or primary threads and from secondary threads to primary threads when possible. These enhancements can help to provide better processor utilization and decrease or eliminate, the effect shown in Table 1.
Random Joe, who is a hardcore gamer, watches some video comparing HT vs no-HT without reading comments and concludes he should disable HT.An engineer looks at a high performance ARM core and a high performance, but slower x86 cores. Sees SMT hardware in one, but none in the other. The engineer writes down his conclusion: when SMT2 hardware is missing, the CPU runs faster.
Random example of 7950X3D, V-cache CCD enabled only, SMT on vs. off:Joke aside, I'm still not convinced of the usefulness or uselessness of SMT.
What Intel basically said is that they are losing about one generation of ST performance by implementing SMT. And it's clear that they can't afford it anymore as there is rivals that goes all in for ST performance.
An engineer examines a locust. First the engineer claps his hands, and the locust jumps. He then proceeds to cut one of it's legs, claps his hands, the locust jumps. He cuts one more leg, claps his hands, the locust jumps no more. The engineer writes down his conclusion: when two legs get cut off, the locust loses hearing capacity.
An engineer looks at a high performance ARM core and a high performance, but slower x86 cores. Sees SMT hardware in one, but none in the other. The engineer writes down his conclusion: when SMT2 hardware is missing, the CPU runs faster.
Joke aside, here's another point of view from IBM:
Thinking as an end customer, this might be important in a hand held gaming console or 5g tablet. Otherwise I am not going anywhere near such a processorThis is not speculation anymore as Intel did provide numbers explaining why they ditch SMT. Yeah, I have liked to speculate that SMT needs additional logic in cpu critical paths and some ST performance is there after abandoning it - but I was in order of magnitude too conservative if those Intel numbers are real.
There is a lot of distance between "you can separate your cores into throughput-efficiency-optimized vs single-thread-optimized in a heterogeneous design" and "SMT categorically considered harmful."
Thinking as an end customer, this might be important in a hand held gaming console or 5g tablet. Otherwise I am not going anywhere near such a processor
Let's talk about those numbers Intel gave. They claim to lose 15% iso-power st speed from SMT design. That's pretty much one giant cpu generational step. They have been trying everything they could to have ST crown - driving unbelievable power limits to the edge of instability and they always had 15% on table from SMT. Thats sure path to lose ST performance crown - which unlike this forum which prefers throughput over anything still the merit which will measure cpu pricing.