Same. Right up until AMD rug pulled TR4 and abandoned any pretense of providing a reliable cadence. Spending that much money and then being stuck in the dark when it comes to upgrade path really sucks.
There was a time until recently where I would’ve picked up a new Threadripper machine with little thought.
I think you're right in your last paragraph but I also think it's something that's been intentional from the start. When they first went to TSMC they were using 7nm, we're only buying leading edge (or close to it) capacity. Now. They can keep premium on leading edge and they already now have a bunch of IP on older, more abundant nodes to churn out volumes for OEM and commercial. Before it would have been more of a gamble. Now they have cheap capacity and reusable IP.Corporate is either "run it until it can't do something we need or is forced to be retired by MS" or it's on a depreciation/warranty schedule and gets replaced every 3-5 years. When they buy, they look at what their minimum baseline performance must be for their current usage and then see how much above that they can afford to buy an extra year or two before being forced to upgrade. I often see a whole lot of i5 level stuff out there, or a mixed environment with a whole lot of i3/Celeron stuff with a small group of nearly top end stuff for power users or people with pull that just want it.
AMD was not serious in this market until Zen4. No iGPU on desktop, save for APUs that were pricey for what you got. Now, they have a broad range of cost competitive APUs and desktop CPUs with usable iGPUs. They just need OEM buy in to finance the volumes they would need.
I was thinking this as well. Corporate might well be satisfied with the price/performance of Zen 5 or even Zen 4.I think you're right in your last paragraph but I also think it's something that's been intentional from the start. When they first went to TSMC they were using 7nm, we're only buying leading edge (or close to it) capacity. Now. They can keep premium on leading edge and they already now have a bunch of IP on older, more abundant nodes to churn out volumes for OEM and commercial. Before it would have been more of a gamble. Now they have cheap capacity and reusable IP.
That's the elephant in the room Intel has kind of avoided to adress so far.Which makes you wonder .... how is Intel going to produce high volume 18A at a low cost for Corporate without going bankrupt doing it?
What Intel sorely lacks right now, in my opinion, are remotely cost-competitive equivalents to TSMC's N6 and N4 processes for mainstream parts (and suitably area/power-efficient core designs for them).
Intel could easily do 2+8 monolithic designs on Intel3 that could yield well and be cost competitive in corporate. They just choose not to.
I was thinking this as well. Corporate might well be satisfied with the price/performance of Zen 5 or even Zen 4.
Unless Zen 6 has a VERY tiny CCX version for corporate (<50mm?), it seems like N3E and especially N2 wouldn't be cost effective for that purpose.
Which makes you wonder .... how is Intel going to produce high volume 18A at a low cost for Corporate without going bankrupt doing it?
... and if their plan is to stick with 13 & 14K, they would be up against Zen 5 which I think is pretty compelling against these older designs ...... especially in laptops.
Raptor Lake has a zero on the AI capabilities, capabilities that are being pitched to corporate customers. Intel will barely get away selling some Raptor Lakes in 2025. There is no way any OEM will put them in their 2026 products.
OEMs are pushing AI because Wall Street orgasms at the mere thought of it. Doesn't mean the OEM's actual customers are interested.
that's not how any of that works.Corporate might well be satisfied with the price/performance of Zen 5 or even Zen 4.
WCL is 2+4 and it's cheap and good. amen.Intel could easily do 2+8 monolithic designs on Intel3 that could yield well and be cost competitive in corporate. They just choose not to.
the CCX can be configured at whatever.Unless Zen 6 has a VERY tiny CCX version for corporate (<50mm?), it seems like N3E and especially N2 wouldn't be cost effective for that purpose.
it's called WCL.how is Intel going to produce high volume 18A at a low cost for Corporate without going bankrupt doing it?
Fair enough.that's not how any of that works.
They buy the laptop, not what's inside it.
what's more PPA-better in this case?Why will the major Laptop OEM's pick a more expensive option vs a more cost effective and power effective one?
Why would the OEM care anything at all about the PPA of a chip inside their product?what's more PPA-better in this case?
Well yeah Zen6 will be better at that. Next.I would imagine it is all about overall cost, power draw, and then performance.
And those sweet, sweet margins selling highest for the lowest parts they can get away with. Mmm, margins.Why would the OEM care anything at all about the PPA of a chip inside their product?
I would imagine it is all about overall cost, power draw, and then performance.
Nice, here's the full release:Not sure if this needed any confirmation but Venice is on N2, officially https://ir.amd.com/news-events/pres...ieves-first-tsmc-n2-product-silicon-milestone
Looks like Venice is on track to launch next year.SANTA CLARA, Calif., April 14, 2025 (GLOBE NEWSWIRE) -- AMD (NASDAQ: AMD) today announced its next-generation AMD EPYC™ processor, codenamed “Venice,” is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2nm (N2) process technology. This highlights the strength of AMD and TSMC semiconductor manufacturing partnership to co-optimize new design architectures with leading-edge process technology. It also marks a major step forward in the execution of the AMD data center CPU roadmap, with “Venice” on track to launch next year. AMD also announced the successful bring up and validation of its 5th Gen AMD EPYC™ CPU products at TSMC’s new fabrication facility in Arizona, underscoring its commitment to U.S. manufacturing.
“TSMC has been a key partner for many years and our deep collaboration with their R&D and manufacturing teams has enabled AMD to consistently deliver leadership products that push the limits of high-performance computing,” said Dr. Lisa Su, chair and CEO, AMD. “Being a lead HPC customer for TSMC’s N2 process and for TSMC Arizona Fab 21 are great examples of how we are working closely together to drive innovation and deliver the advanced technologies that will power the future of computing.”
“We are proud to have AMD be a lead HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona fab,” said TSMC Chairman and CEO Dr. C.C. Wei. “By working together, we are driving significant technology scaling resulting in better performance, power efficiency and yields for high-performance silicon. We look forward to continuing to work closely with AMD to enable the next era of computing.”
Not sure if this needed any confirmation but Venice is on N2, officially https://ir.amd.com/news-events/pres...ieves-first-tsmc-n2-product-silicon-milestone
Yeah they like the stuff.that AMD will be the leading customer on N2.
Turin.Also, in the press release, it says Genoa from TSMC Arizona fab has been validated.
Turin.
That is what I want to know most how many cores on a single CCD and if there will be an increase in 1:1 speed so higher speed DDR5 can be used.Oops, you are correct, that is Turin, they are talking about, being produced in TSMC Arizona plant.
Good call on Zen 6 N2.
I wonder what the packaging technology will be for Venice. Very likely, different from client, which means sharing of CCDs will no longer be taking place.
As far as Venice, I also wonder if the classic Zen 6 CCD will be 12 or 16 cores. Then, Dense likely at 32 cores.
Although, MLID said that on future roadmaps, AMD is not differentiating between classic and dense cores for servers.
Nice, here's the full release:
Looks like Venice is on track to launch next year.
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