Question Zen 6 Speculation Thread

[Joe NYC]

SP7 - That should be new socket for Zen 6 - Venice:

https://twitter.com/x/status/1859979783092031729

 

[FlameTail]

Will Zen6 APUs (Medusa) have RDNA4 or RDN A5 UDNA?

 

[inquiss]

Will Zen6 APUs (Medusa) have RDNA4 or RDN A5 UDNA?

The latter. AFAIK RDNA 4 is not in any APU product

 

[techjunkie123]

Came across this on Reddit. No clue if it is correct, but if so, I wonder is 12 core CCXs with smaller cores are for server. Maybe desktop/mobile will use a different design?

 

[FlameTail]

• Small IPC gain (10%)
• Major node shrink (4nm -> 3nm)

It will not surprise me that the cores are smaller.

 

[marees]

Will Zen6 APUs (Medusa) have RDNA4 or RDN A5 UDNA?

I wouldn't be surprised if it is RDNA 3.5

 

[Kepler_L2]

Will Zen6 APUs (Medusa) have RDNA4 or RDN A5 UDNA?

It's a mix AFAIK, but most are using a slightly upgraded RDNA3.5 uarch.

 

[gdansk]

It's a mix AFAIK, but most are using a slightly upgraded RDNA3.5 uarch.

RDNA3.5 (or 3.75) in 2027? It's like Vega all over again.

 

[marees]

RDNA3.5 (or 3.75) in 2027? It's like Vega all over again.

Were you hopin/plannin on running Alan Wake 2 with path tracing on a zen 6 APU 🤪

 

[Gideon]

Were you hopin/plannin on running Alan Wake 2 with path tracing on a zen 6 APU 🤪

I really hope the Halo parts at least have UDNA. 40+CUs is definitely capable of RT (though probably nit path tracing)

 

[Meteor Late]

Also it's important to have the latest decoders, having Vega for so long meant that some products, even last year, still lacked AV1 decode, for example 7530U.
With VVC we could have the same situation in 2027.

 

[OneEng2]

12 core CCD's sounds reasonable for desktop and high performance laptop; however, I believe that half that (6 CCD) would be more than enough for many budget applications.

Seems like a 2 CCD 24 core 48 thread desktop Zen 6 would be quite a beast.

 

[FlameTail]

12 core CCD's sounds reasonable for desktop and high performance laptop; however, I believe that half that (6 CCD) would be more than enough for many budget applications.

Seems like a 2 CCD 24 core 48 thread desktop Zen 6 would be quite a beast.

If the flagship is getting a 50% core count increase (16->24), then it's worth increasing the entry level part to 8 cores (33% increase, 6->8).

 

[adroc_thurston]

With VVC we could have the same situation in 2027.

VVC is DOA like any other MPEG-LA codec since the dawn of AV1.

Will Zen6 APUs (Medusa) have RDNA4 or RDN A5 UDNA?

RDNA5 where it matters, 3.5 for luggables etc.

12 core CCD's sounds reasonable for desktop and high performance laptop

If it's real, it's probably something like 6C+6c ring layout.

 

[marees]

If the flagship is getting a 50% core count increase (16->24), then it's worth increasing the entry level part to 8 cores (33% increase, 6->8).

How ryzen r3 phenom for six cores ?

 

[OneEng2]

I am thinking that AMD would want to communize as many chiplets as possible for economy of scale and flexible manufacturing purposes.

I believe that today, desktop CCD's are all 8 cores. I think the 6 core variants are simply 8 core CCD's with 2 cores disabled (due to defects I suspect).

If Zen 6 has 12 core CCD's, then the lineup would look like:

Top end: 2x12 CCD's
Mid range: 1x12 CCD
Budget: 1x12 CCD with 8 or 10 active cores.

Now the idea of having a mix of Zen 6 and Zen 6c in the CCD is a very interesting idea. It also complicates the models as now you can have a wide combination of P core count and E core count combinations depending on configuration and chiplet yield.

The server tiles would, of course, be larger (32 core CCD's up from the current 16 core CCD's).

 

[CakeMonster]

I'm not overly optimistic about more cores per CCD because of the skyrocketing node cost and the slow advancement lately (except for the c core parts).

 

[OneEng2]

I'm not overly optimistic about more cores per CCD because of the skyrocketing node cost and the slow advancement lately (except for the c core parts).

Fair point in desktop and laptop.

 

[soresu]

Budget: 1x12 CCD with 8 or 10 active cores.

We'll probably see some with 6 too, unless their yields are too good to make it worthwhile.

 

[soresu]

I'm not overly optimistic about more cores per CCD because of the skyrocketing node cost and the slow advancement lately

Bearing in mind that core count per CCD hasn't actually changed since Zen1 in consumer land.

aka since 14nm finfet.

A 50% boost is definitely within the realms of possibility at this point when we are on the verge of 2nm nanosheet nodes.

 

[RnR_au]

A 50% boost is definitely within the realms of possibility at this point when we are on the verge of 2nm nanosheet nodes.

But does 12 cores make sense from a consumer perspective? And when you have Zen 6c cores available?

Wasn't there some speculation/rumour that in consumer land everything will mostly be mobile apu based? Only serverside will have 'raw' ccds?

Or was that an iffy thought?

 

[maddie]

Bearing in mind that core count per CCD hasn't actually changed since Zen1 in consumer land.

aka since 14nm finfet.

A 50% boost is definitely within the realms of possibility at this point when we are on the verge of 2nm nanosheet nodes.

How does this work with AM5? Already we see Zen5 as having some main memory limitations.

If we have a 50+ % increase in cores and another 10+ % throughput increase per core, where does that leave us? DDR5 10000+ needed?

As a comparison, SP5 has 12 channels serving 128 Zen5 cores vs AM5 having 2 channels with 16 cores maximum.

 

[RnR_au]

How does this work with AM5? Already we see Zen5 as having some main memory limitations.

If we have a 50+ % increase in cores and another 10+ % throughput increase per core, where does that leave us? DDR5 10000+ needed?

As a comparison, SP5 has 12 channels serving 128 Zen5 cores vs AM5 having 2 channels with 16 cores maximum.

Strix Halo has been mentioned in the past on these forums as being a 'pipe cleaner' of tech that is being rolled out to Zen 6 consumer sku's. So there is a doubling of membw if the Strix Halo rumours are correct.

 

[moinmoin]

How does this work with AM5? Already we see Zen5 as having some main memory limitations.

The bottleneck is not the memory speed or even IF speed but the link between CCD and IOD. Design wise CCDs are capable of two such links but in client chips only one is ever used.

 

[maddie]

Strix Halo has been mentioned in the past on these forums as being a 'pipe cleaner' of tech that is being rolled out to Zen 6 consumer sku's. So there is a doubling of membw if the Strix Halo rumours are correct.

Yes, Strix Halo will answer many questions.

The bottleneck is not the memory speed or even IF speed but the link between CCD and IOD. Design wise CCDs are capable of two such links but in client chips only one is ever used.

True, but the SP5 socket has max 10.67 cores/memory channel, also slower cores, still 50% more bandwidth/core than AM5 (max). Tells me, that at the limit, the cores with AM5 are starved. Strix Halo will show what's true.