Question Zen 6 Speculation Thread

[adroc_thurston]

Who the hell sent this to him.

Says AMD "likes" N2 for CCDs.

Better, they like it in N2X flavour.

Also said that IOD may be more advanced node.

It is. For Medusa premium/halo.

 

[reaperrr3]

Better, they like it in N2X flavour.

If that's true, it would suggest they're going for (notably) higher clocks, given the X nodes are basically leakier node variants geared towards higher voltages and clocks.
Would be a little surprising for a CCD that's meant to be used for APUs as well, but maybe N2X is actually still efficient enough at more modest clocks/voltages?

 

[adroc_thurston]

given the X nodes are basically leakier node variants geared towards higher voltages and clocks.

well yeah that's what everyone's gonna be doing.

 

[StefanR5R]

Says IOD still TSMC (there was some speculation on Twitter today it may be Samsung),

Elsewhere a rumor was discussed that Samsung could enter as a second maker of sIODs, not cIODs. [Edit: They also point out the idea of a Samsung manufactured client southbridge, i.e. Promontory 21 successor. Edit 2: More importantly, they point out that the origin of this rumor is in Korea…]

Re sIOD: I am thinking, the 8004 and 9004 lines have the same IOD and 9005 has got a new one — now if 8004 gets an update or a successor, perhaps AMD would design an extra IOD for it, different from the 9005 successor's rather than a ~half disabled one. After all, as the top end of server chips crams more and more CPU and IO into a single socket, the market for separate mid-size server sockets is bound to expand.

 

[poke01]

So next year every CPU in 2026 gonna be on some N2 variant? NVL, Zen6, QC X Elite and M6.

I don't think we ever had that before

 

[Win2012R2]

Sounds great, but what are the chances of getting first new transistor upgrade since FinFets right on the first attempt in N2? Seems impossible...

 

[RnR_au]

So next every CPU is in 2026 gonna be on some N2 variant? NVL, Zen6, QC X Elite and M6.

I don't think we ever had that before

Will TSMC even have enough N2 capacity to keep all these happy?

 

[poke01]

Will TSMC even have enough N2 capacity to keep all these happy?

hope so, i don't want a shortage on CPUs too. lol

 

[adroc_thurston]

Will TSMC even have enough N2 capacity to keep all these happy?

Yea.

 

[LightningZ71]

Somehow I doubt that AMD will completely skip the N3 flavors for everything that's not Turrin-dense. I still feel that there's going to be a Kraken Point successor or other lower end product that's on N3P.

 

[Timorous]

L3 Cache width is almost identical to current CCD so this is definitely 48MB.

With the cache die being under the CCD I presume that gives almost 75mm of area for the cache which is plenty for 96MB or even 144MB depending on how dense and how large they want cache dies to be.

Of course with lower latency to ram and hopefully higher bandwidth as well maybe v-cache will make less difference on Zen 6 than it does with prior iterations.

 

[jpiniero]

Somehow I doubt that AMD will completely skip the N3 flavors for everything that's not Turrin-dense.

It'll definitely be eggspensive if true.

 

[StefanR5R]

with lower latency to ram and hopefully higher bandwidth as well maybe v-cache will make less difference on Zen 6 than it does with prior iterations.

RAM access latency is basically governed by DRAM access latency, and this hasn't improved substantially for ages now and won't do so going forward, right? The new RDL interface will facilitate high bandwidth at lower on-package energy cost, and that's it basically.

[For dual-CCD processors it perhaps reduces latency of cache probing (what's definite is that it reduces energy cost of cache probing), which would help with atomic memory accesses and everything which is built on atomics: Locks, fundamentally. But if performance of an algorithm is determined by lock performance, look for possible optimizations of the algorithm first, before you look for hardware optimizations. — But AFAICT this is unrelated to whether or not V-cache keeps making a difference to degrees as it did for Zen 3…5.]

 

[GTracing]

It'll definitely be eggspensive if true.

Not necessarily. An 85mm^2 CCD on N2 would be ~$50. That's with a $30000 wafer price and 0.1 defect density. The CCDs are a small fraction of the overall cost of the CPU.

Intel is offering high core counts for relatively cheap. AMD might be forced to keep their prices sane.

 

[techjunkie123]

Did anyone try estimating the Zen 6 core size and xtor # from the leak?

 

[Tuna-Fish]

RAM access latency is basically governed by DRAM access latency, and this hasn't improved substantially for ages now and won't do so going forward, right? The new RDL interface will facilitate high bandwidth at lower on-package energy cost, and that's it basically.

There is a noticeable latency penalty caused by the SERDES, and it is basically the difference in memory latency between Intel and AMD. A wider interface can remove the need for serialization, and thus reduce the latency.

Most of the total access latency is DRAM latency, but that doesn't mean that the smaller parts don't matter. Latency is additive.

 

[eek2121]

Some interesting things I wish AMD would try:

1) A v-cache part with v-cache that is shared between 2 CCDs.
2) A dual CCD part where 1 CCD is all P-cores and the second is all C cores. The second die could have more cores as a result.
3) A large-ish, low latency last level cache on the IOD.
4) Triple CCD part 2 of the CCDs are full of C-cores while one has P-cores.

One can dream! 🤣

Fair enough, but if the 12 core rumor has the same amount of caveats, then we should assume the worst for all possible unknowns. The 12 core CCD exists, but 8 of the 12 cores are dense and only clock to 4GHz, and the L3 cache per core is cut in half, and the AVX pipeline is double pumped.

AMD basically HAS to bump up the core count for competitive reasons. Intel is doubling their core counts, and I question whether even a 12 core CCD would be enough.

I hadn't considered the possibility that each CCD could be a mix of different core types. AMD has certainly done that before. If they keep the same size ratio between the cores, they could do 6 P cores and 6 C cores and only grow the physical dimensions just a little while also keeping the L3 cache at 32MB. I don't necessarily think that they would want to do 4+8 as that may not game bench as well, but doing so would almost preserve the same footprint as 8 P cores. Comparing the 9700x to the AI 370, the vast majority of the performance difference between the two is caused by the lower clocks of the 370, the larger L3 of the 370, and everything being on one CCX. If AMD had done a 12 core Zen5 CCX with 4 + 8, the ST would be the same and the MT for it would likely be higher for that as compared to the 9700x.

That's a very interesting thought...

I would be surprised if they DID’T use C-cores. I think we’ll see at least 4. Admittedly I haven’t been following any of this stuff about Zen 6, however.

Elsewhere a rumor was discussed that Samsung could enter as a second maker of sIODs, not cIODs. [Edit: They also point out the idea of a Samsung manufactured client southbridge, i.e. Promontory 21 successor. Edit 2: More importantly, they point out that the origin of this rumor is in Korea…]

Re sIOD: I am thinking, the 8004 and 9004 lines have the same IOD and 9005 has got a new one — now if 8004 gets an update or a successor, perhaps AMD would design an extra IOD for it, different from the 9005 successor's rather than a ~half disabled one. After all, as the top end of server chips crams more and more CPU and IO into a single socket, the market for separate mid-size server sockets is bound to expand.

They have been in discussions with Samsung for quite a while, yet nothing has come of it. We will see.

 

[adroc_thurston]

They have been in discussions with Samsung for quite a while

not even, actually engaged with the PDKs.
Sonoma Valley should be the first (modern) SS node product.

 

[jpiniero]

AMD basically HAS to bump up the core count for competitive reasons. Intel is doubling their core counts, and I question whether even a 12 core CCD would be enough.

Intel can add all the cores they want, gaming performance is what matters to DIY.

That applies to Zen 6 as well. Granted I don't think AMD would be that upset if people bought 9800X3D instead if Zen 6 fails to deliver in gaming.

 

[Kepler_L2]

Did anyone try estimating the Zen 6 core size and xtor # from the leak?

It looks around 12% smaller. Using TSMC numbers for logic and SRAM scaling, and assuming 50/50 between Logic and SRAM, it's around 32% more transistors.

 

[OneEng2]

So next year every CPU in 2026 gonna be on some N2 variant? NVL, Zen6, QC X Elite and M6.

I don't think we ever had that before

I don't believe that at all. I suspect that AMD will keep desktop and EPYC workstation on N3P. Models where max core count and density outweigh max performance per core (like laptop and EPYC Dense) will use N2. This would be consistent with the current Zen 5 model. I could be wrong, but this is how I am reading the tea leaves at present .

Somehow I doubt that AMD will completely skip the N3 flavors for everything that's not Turrin-dense. I still feel that there's going to be a Kraken Point successor or other lower end product that's on N3P.

I agree. Maybe include high end laptops too .... but maybe not.

AMD basically HAS to bump up the core count for competitive reasons. Intel is doubling their core counts, and I question whether even a 12 core CCD would be enough.

16P + 32E + 4 ELP.

Currently in MT workloads (due to SMT in Zen 5), 1 Zen 5 = 1.3 Intel P or 1.5 Intel E. Perhaps 2 Intel ELP? Lets just say that the Intel and AMD performance lifts equal out and the ratio stays the same.

16P / 1.3 = 12.31
32E / 1.5 = 21.3
4LPE / 2 = 2

So AMD would need a 36 core processor with Zen 6 to match the 54 core monster.

Since AMD IS creating a 32 core CCD on 2nm for EPYC (I believe), a pair of those on the desktop would totally and completely wipe out the highest end Nova Lake ..... but my guess is that this would not be considered a desktop standard offering, but rather a version of Thread Ripper.

 

[DavidC1]

I don't know why Intel is doubling the cores on Nova Lake. We're unlikely going to see anywhere near 2x the gain, since they're already power limited with Arrowlake.

 

[LightningZ71]

The other thing that keeps coming to mind are the relatively modest gains for Zen6 over Zen5 (edited: originally had Zen6 twice) that were forecast on that slide that was circulated last year. They were barely looking to get 10% it seemed. Going from N4P to N3P and including fin flex where it can help should be able to net a good 5+% clock speed or more while also improving the power characteristics which would allow additional all core clock speed. Couple that with better memory access latency numbers due to a new IOD and inter die connection and I don't see where the need for N2 is really pressing.

The math ain't mathing for me...

 

[Thunder 57]

I don't know why Intel is doubling the cores on Nova Lake. We're unlikely going to see anywhere near 2x the gain, since they're already power limited with Arrowlake.

It is just a rumor, right? Honestly doesn't make much sense to me either unless they cut power way down.

 

[Saylick]

… relatively modest gains for Zen6 over Zen6 that were forecast on that slide that was circulated last year. …

The math ain't mathing for me...

Your math ain’t mathing for me, either.