Question Zen 6 Speculation Thread

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Markfw

Moderator Emeritus, Elite Member
May 16, 2002
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We will see what emerges, on the server side. AMD has been on the same technology since Rome, since 2019, and in 2026, it will be 7 years.

7 years was a plenty of time to plan the new architecture, it will be interesting to see it unveiled.

If the original idea (of 4 IODs each forming a unit with 2 CCDs) was to be implemented, it would be possible to do it using the same technology as Strix Halo, the carrier wafer size would not be too much bigger than the one for Strix Halo.

And then it showed some bridges to connect the IODs, that would have to use a different technology, maybe hybrid bond silicon bridges.

(this is the picture from the old video)
View attachment 122181
Regardless of your picture, in 7 years the performance has GREATLY increased. From Naples to Turin. And I have owned all of them. I still have Rome, Milan, Genoa and Turin !!! I would have to check the benchmarks, but on the order of 2x to 3x. (depending on what type of code is executed)
 
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Hulk

Diamond Member
Oct 9, 1999
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If we had compute 4000 years ago we might not have the pythagorean theorem. Why go through the work of figuring that out when you can just throw millions of cycles at finding the length of the hypotenuse?

Just kidding of course. Or more to the point I'm being "hyperbolic" in making the point that I'm concerned that AI and the availability of so much cheap compute means there is no need to push the human brain to do the amazing things it has done before logic circuits were developed.

Sometimes limitations are good. How many times have you had a problem or issue that just couldn't be solved but you found a way?! My mantra has always been "one impossible problem at a time." That's how you climb the mountain that can't be climbed.
 

eek2121

Diamond Member
Aug 2, 2005
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Regardless of your picture, in 7 years the performance has GREATLY increased. From Naples to Turin. And I have owned all of them. I still have Rome, Milan, Genoa and Turin !!! I would have to check the benchmarks, but on the order of 2x to 3x. (depending on what type of code is executed)
What blows my mind is seeing my 7950X casually beating my 1950X in benchmarks like Cinebench while using less power.
 

Kronos1996

Member
Dec 28, 2022
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No cache or interconnect variants?
Shouldn’t be a need. All of them will be using the same packaging this time, similar to whats in Strix Halo. That’s the only reason Halo had a different CCD this time. All vanilla CCD’s are equipped with TSV’s for 3D cache so I doubt that changes.

I don’t see why they’d need a 3rd CCD type except for a few niche reasons:

1 - Mixed-core CCD for some mobile products. I could see a 4 + 8 Zen 6/6C CCD for low-end mobile. More than likely they’ll stay monolithic for dies that small though. Should be cheaper than advanced packaging.

2 - If there’s meaningful benefit from a mobile optimized CCD targeting lower voltage and other minor efficiency improvements. Highly doubt that would provide much for the cost though.

3 - They want a larger core-count Zen 6 CCD for Epyc so they can fit more cores into the same packaging layout. Zen 6C CCD reportedly having 32 cores may lend some credibility to this idea? I’m sure they want to reuse the same package for both. If each version of Epyc has a different number and/or placement of dies (due to size differences), that would require two different packaging designs I think. They’re using embedded bridges so exact placement is very important.
 

Tuna-Fish

Golden Member
Mar 4, 2011
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Shouldn’t be a need. All of them will be using the same packaging this time, similar to whats in Strix Halo. That’s the only reason Halo had a different CCD this time. All vanilla CCD’s are equipped with TSV’s for 3D cache so I doubt that changes.

Note that starting with Zen5, the TSVs don't go on the CCD. The CCD is face down on top of the cache chiplet, so no holes need to be drilled through its substrate. They just need to add vias and pads through the metal layers for the interconnect, and these don't need extra manufacturing steps. This moves the silicon cost for x3D from the CCD to the cache die, which facilitates sharing chiplets.
 
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Markfw

Moderator Emeritus, Elite Member
May 16, 2002
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What blows my mind is seeing my 7950X casually beating my 1950X in benchmarks like Cinebench while using less power.
Speaking of which, how much to you think 70 12 core Xeon cloud servers cost to power vs 6 AMD Genoa 64 core and one Zen 5 64 core ?

And thats not a typo. even of that was /5 thats 14 Xeon vs 7 AMD mostly Zen 4. I have a post in DC, but thats what it took to beat by little farm. 89 servers 70 of which are cloud 12
cores.

And not that anyone here cares, but my Genoa Zen 4 work computer found the 16th largest prime number in the world.
 

Doug S

Diamond Member
Feb 8, 2020
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10mhz audio? I don't think that's a thing.

Exactly, I was saying that DIDN'T happen because humans can't hear in the hundreds of thousands let alone millions of hertz. Likewise we won't keep increasing resolution higher and higher without end and follow 4K with 8K then 16K and so on.

But we'll keep making storage devices bigger and bigger without any natural limit because they aren't limited by humans (i.e. no one is required to sit there and read through terabytes of information stored on a hard drive) so long as there is value derived from storing more data.
 

Joe NYC

Platinum Member
Jun 26, 2021
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Shouldn’t be a need. All of them will be using the same packaging this time, similar to whats in Strix Halo. That’s the only reason Halo had a different CCD this time. All vanilla CCD’s are equipped with TSV’s for 3D cache so I doubt that changes.

I don’t see why they’d need a 3rd CCD type except for a few niche reasons:

1 - Mixed-core CCD for some mobile products. I could see a 4 + 8 Zen 6/6C CCD for low-end mobile. More than likely they’ll stay monolithic for dies that small though. Should be cheaper than advanced packaging.

With LP cores, the need to spam Zen 6c cores diminishes. Jumping from N4 to N2, full Zen 6 core will already have a good efficiency improvement.

2 - If there’s meaningful benefit from a mobile optimized CCD targeting lower voltage and other minor efficiency improvements. Highly doubt that would provide much for the cost though.

That would benefit full cores as well, so again, less need for dense cores.
 

Hulk

Diamond Member
Oct 9, 1999
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A PII-500 cost $655 in 1999 or over $1400 today with inflation. You could buy 2 9950X's with that money and the compute is orders of magnitude greater.

Let's jump ahead 10 years. In 2010 the 980X Extreme was top dog with 6 cores and it cost $955, or about $1400 in todays' money. Increase in compute is enormously greater.

10 more years to 2020 and you have the 5950X at $799 or about $900 in today's money. The 9950X is more performant and cheaper and that is only a 4 year time frame from the time of the 9950X release.

I have demonstrated noticeable improvements in both cost and performance going back 26 years, 15 years, and 4 years and in all cases you CAN buy more compute not only for the same money but for LESS money.

Compute IS getting cheaper every year. It might not feel that way because developers are finding ways to use to use those cycles but that does not make the fact not true.

If you want to argue about the rate that compute is getting cheaper then fine we can have that discussion and someone can take the time to chart compute vs. time vs. price.

But that is not my point. My point it that it is getting cheaper every year and it is cheap.

Think about it this way. If a processor generation only shows 5% overall increase in compute from the previous generation but price remains the same, then with inflatation factored in, not only has performance increased, but price has decreased.

Finally, just to drop the mic, in 1990 a 486 DX33 (top dog) cost $900 or about $2300 today. Yes, compute is cheap and getting cheaper every year.

Moore's "law" isn't the only factor for compute price and it slowed but hasn't stopped.

 

basix

Member
Oct 4, 2024
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Cost per xtor is going *up*.
A few people say that. But because it is not reflected in customer product prices I highly doubt that:
  • 6700XT, 12GB, 480$, 17.2 bTr, 335mm2, N7
  • 7800XT, 16GB, 500$, 28.1 bTr
  • 9070XT, 16GB, 600$, 53.9 bTr, 357mm2, N4
So we have here 1.3x MSRP increase with 1.33x VRAM and 3x transistors. With the difference of N7 vs. N4 in between. Chip size of N22 is similar to N48 and because N48 is sligthly bigger, somewhat higher costs can be assumend. And yet, consumer prices are very similar. There is no chance, that per-xtor cost has gone up because otherwise AMD would sell N48 cards at a loss.
So as a result, I definitely do not see any evidence of cost per-xtor going up. Same applies for CPUs, where transistor count has increased by a lot as well (looking at Zen 3 to Zen 5). All in all a very similar situation as observed for GPUs:
  • 5700X, 300$, Zen 3 CCD, 4.15 bTr, 80.7mm2, N7 / 2.09 bTr 12nm IOD
    • I exclude the 450$ 5800X here
  • 9700X, 360$, Zen 5 CCD, 8.32 bTr, 70.6mm2, N4 / 3.4 bTr 6nm IOD
We do not know the trends for N3 or N2 yet, but looking at Apples M3 and M4 and their Mobile SoC siblings, I do not expect massive price increases as well. Cost per area goes up, for sure. There is no doubt about that. But per-xtor is the chance very close to zero.
 

OneEng2

Senior member
Sep 19, 2022
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If we had compute 4000 years ago we might not have the pythagorean theorem. Why go through the work of figuring that out when you can just throw millions of cycles at finding the length of the hypotenuse?

Just kidding of course. Or more to the point I'm being "hyperbolic" in making the point that I'm concerned that AI and the availability of so much cheap compute means there is no need to push the human brain to do the amazing things it has done before logic circuits were developed.

Sometimes limitations are good. How many times have you had a problem or issue that just couldn't be solved but you found a way?! My mantra has always been "one impossible problem at a time." That's how you climb the mountain that can't be climbed.
I taught my kids to memorize our phone number. Now, the only phone number I know is my wife's and mine .... and only because they are both used for store accounts (Kroger and CVS ). Otherwise, I might not even remember those .

You have a good point though. I have actually argued the opposite in the framework of engineering. I have been designing and running design teams for decades. My youngest daughter is taking Calc III right now for her ME degree. I couldn't do a triple integral if my life depended on it . I can do some pretty scary FEA on CAD, and can make SPICE jump through hoops for circuit analysis.

Does this mean I am no longer a good engineer though? I simply have better tools than I had 40 years ago to solve problems with.

FWIW, I still use the pythagorean theorem and SOH, CAH, TOA (Soak-ah-toe-ah) .
Exactly, I was saying that DIDN'T happen because humans can't hear in the hundreds of thousands let alone millions of hertz. Likewise we won't keep increasing resolution higher and higher without end and follow 4K with 8K then 16K and so on.
Ironically, there is still wild debate in the digital mixing world about the benefits of 96Khz vs 48Khz processing. Even with the Nyquist theorem, 48Khz can reproduce 24Khz sound perfectly. Shoot, I am lucky to hear 16Khz these days .
With LP cores, the need to spam Zen 6c cores diminishes. Jumping from N4 to N2, full Zen 6 core will already have a good efficiency improvement.
I wonder how useful LP cores are though compared to the utility of a Zen 6c? Cores are getting so small that unless you have a butt ton of them, you spend more size on other things. In desktop, I just wonder how important it is to have more than 16 cores, especially with 32T? Also, with super high core counts comes the need to feed all these cores with more memory controllers and more memory channels. All of these things smack of HPC like Threadripper to me.

In very high core count applications, I think you end up being power and bandwidth limited per socket. In order to get around the problem, you need a bigger socket with more pins and more power.
It's literally the only factor and it has not only slower, it's reversing.
Cost per xtor is going *up*.
No it's not. Chiplet technology, packaging, memory speed, and a bunch of other technologies are all outside Moore's law and contribute greatly to performance/$
 
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Abwx

Lifer
Apr 2, 2011
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A PII-500 cost $655 in 1999 or over $1400 today with inflation. You could buy 2 9950X's with that money and the compute is orders of magnitude greater.
It was the PIII-500 since it was in competion with the Athlon 500-600, IIRC the PII topped at 450MHz, neverless the actualised price equivalence is still relevant
 

Doug S

Diamond Member
Feb 8, 2020
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It's gotten cheaper because moore's law.
Moore's law is very very very dead.

Computing is still getting cheaper. Moore's Law isn't dead, its just slowing down.

Compare what you could buy for $500 or for $5000 five years ago with what you can get today. Can you not get more and faster cores, better GPUs, more RAM and bigger/faster SSDs at those same $500 and $5000 price points? Can you not build more server capacity (vCPUs, gigabytes of RAM, terabytes of storage) per dollar than five years ago?

So explain why you think it is getting more expensive? That's only true if your needs and wants are growing faster than the above improvements are happening, which doesn't mean computing is getting more expensive it means YOU are getting more expensive!
 

Joe NYC

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I wonder how useful LP cores are though compared to the utility of a Zen 6c? Cores are getting so small that unless you have a butt ton of them, you spend more size on other things. In desktop, I just wonder how important it is to have more than 16 cores, especially with 32T? Also, with super high core counts comes the need to feed all these cores with more memory controllers and more memory channels. All of these things smack of HPC like Threadripper to me.

I think MLID is also confused about utility of the LP cores in modern client computers. Their role is to keep the lights on the PC, while in idle and light loads, and allowing the full speed core complex to shut down.

What is not the role of the LP cores is to meaningfully add to Cinebench scores. Usefulness of the dense cores, like Zen 6c is to improve the Cinebench benchmark, as their primary role.

There may be a whole new role for the LP cores in server environment - as alternative to Arm cores, for very light loads, but that is unrelated to client.
 

adroc_thurston

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basix

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No because GPU is more than just the KGD in its center.
If you would deliver arguments instead of 1-liners without any meaningful content....

Lets take Sapphire 6700XT Pulse vs. 9070XT Pulse. Same manufacturer. Same device class. Same device branding.
- 480$ vs. 600$ -> 1.25x
- 335mm2 vs. 357mm2 -> 1.07x
- N7 vs. N4 -> according to AMD 1.2...1.3x or so (some uncertainty there)
- 12GB 16Gbps GDDR6 vs. 16GB 20Gbps GDDR6 -> 1.33x with higher speeds (but memory should have gotten a little bit cheaper per gigabyte)
- 2-fan vs. 3-fan -> 1.5x
- 230W vs. 304W -> 1.32x
- 9+2 vs 11+3 VRM phases
- PCB size got actually shorter, but maybe 2 layers more

So everything I see there has roughly linearly increased with MSRP. The GPU Die could be a little bit more expensive than the MSRP increase would indicate, hence slightly reduced margins per card might be true. But if the case, not by much.

And now for you to understand:
This is not a per-xtor comparison. This is a component cost comparsion. That is something completely different. 3x more transistors at 1.25x higher price cannot be compensated by other components or less margin. But if you think that is possible, please provide us a explanation or calculation of that.

We have following metrics:
1) Cost per Die area -> goes up
2) Cost per xtor -> goes down, much more than 1)
3) Cost per performance -> goes down, but slower than a few years ago because 1) and 2) work against each other

Moore's Law as it was defined in the 60's and 70's is dead, yes. It is not a doubling of transistors every 12...24 months at the same costs. But transistor cost still goes down.
- Just as a side note here : Moore's Law was mainly a consequence of Dennard's Scaling. That is the true physical effect and foundation behind Moore's more business related prediction. Dennard's Scaling ended ~2005
In the early days, this doubling of transistors resulted in a doubling of performance as well. This has slowed down even more than the transistor cost decrease, see 3) above. But still, performace per cost goes up. In some areas even more than Moore's Law (when accelerators get introduced for some task or ML/AI renders all existing approaches ineffective and useless).
 
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