Question Zen 6 Speculation Thread

[kir123]

Apparently, this is Turin-Dense:
View attachment 122320

Sorry for being a noob. What is that interface in the bottom left corner of die?Intel die doesn't have that.

 

[MS_AT]

What I do find interesting is that CB23 still favors Zen 5 I believe. It makes me think that perhaps CB24 is perhaps more bandwidth dependent vs compute dependent.

Has been confirmed by C&C years ago.

 

[Hulk]

Depend of the CB version, beside it s easy to do slightly better if you use 240W instead of 200W, i wouldnt call this a win.

No, it's a win for ARL.

Stock-for-stock 285K is more performant than 9950X in CB.

I have a 9950X but will admit to the facts. Overall, the 9950X is more performant, which is why I built around it, but not in CB and a few other apps.

 

[fastandfurious6]

That ends up being an operating system benchmark.

benchmarks already have large difference between windows and linux due to cpu schedulers

mac is irrelevant because Mx

logically the cpu running faster in one OS will run faster in the other too




there should be a serious review putting 285K v 9950X in scenarios where real speed is measured beyond CB GB. I have strong suspicion intel works HARD to win CB GB #1 bc they've been behind for many years now but doesnt translate to real advantage

 

[OneEng2]

there should be a serious review putting 285K v 9950X in scenarios where real speed is measured beyond CB GB. I have strong suspicion intel works HARD to win CB GB #1 bc they've been behind for many years now but doesnt translate to real advantage

There are many reviews that showed that in general real world applications, the 9950X outperforms 285K in multi-treaded applications handily.... just not CB24.

 

[StefanR5R]

Apparently, this is Turin-Dense:
View attachment 122320

Interesting. I was certain that the 2nm Turin D would be a 32c CCD using Zen 6c cores while the standard Turin would be 16c of full Zen 6.

Are you certain?

Turin is Zen 5, Venice is going to be Zen 6.
I presume the Turin-dense die shot only went by mistake into the Zen 6 thread.

 

[Hulk]

benchmarks already have large difference between windows and linux due to cpu schedulers

mac is irrelevant because Mx

logically the cpu running faster in one OS will run faster in the other too




there should be a serious review putting 285K v 9950X in scenarios where real speed is measured beyond CB GB. I have strong suspicion intel works HARD to win CB GB #1 bc they've been behind for many years now but doesnt translate to real advantage

9950X is more performant overall. They are close enough where if you had a few apps you specifically needed to maximize you could go one way or the other.

 

[Abwx]

No, it's a win for ARL.

Stock-for-stock 285K is more performant than 9950X in CB.

I have a 9950X but will admit to the facts. Overall, the 9950X is more performant, which is why I built around it, but not in CB and a few other apps.

View attachment 122336
View attachment 122337

Only with CB2024 wich seems ultra optimised for ARL, with R23 and R15 it win only due to 20% higher power.

 

[StefanR5R]

I wonder how many IOd and CCd variants are planned then.

CCD? Probably two.

- Zen 6
- Zen 6C

IOD? Probably four.

- Desktop
- Server
- Medusa (Laptop)
- Medusa Halo

There’s rumors of two desktop IOD’s. A fancy new 3nm one with the Neural Engine and maybe more CU’s. Plus a cheap 6/4nm one for low-end products that’s stripped down. Not sure, we’ll see.

No cache or interconnect variants?

Shouldn’t be a need.

Remember, already in the Zen 5 generation, there are four different CCDs:
– three very similar but not same 8-core CCDs: Ryzen 9000's, Turin's (with allegedly different transistor tuning), and Strix Halo's (without SERDES for IFoP)
– one 16-core CCD: Turin-dense's
Plus two(?) monolithic APUs (Strix Point, Krackan).

Also remember, in the Zen 4 generation, AMD diversified EPYC into several series (Genoa/Genoa-X/Bergamo = EPYC 9004/9004X/9704, Siena = EPYC 8004, Raphael = EPYC 4004) while also keeping Milan = EPYC 7003 alive for a more cost-sensitive midrange server segment, *and* they had the two seemingly one-off Zen 4 EPYCs named MI300A and MI300C. Plus the Threadripper Pro and Threadripper offshoots.

Of all these series, only Genoa and Bergamo had successors in the Zen 5 generation (yet), in the forms of Turin and Turin-dense. But that surely doesn't mean that all the other segments have been abandoned. Eventually, there will be Siena successors (edge/ telco), they are just on a slower cadence than mainline server CPUs. Also, with per-socket throughput and bandwidth and power target growing larger and larger at the top end, more room will be left for spiritual EPYC 7003 successors (edge if you will, but general purpose). I am guessing that the Zen 6 generation will again bring updates in the various server segments outside of general-purpose-top-end and "cloud native".

All of the Zen 4 server CPU lines were made with just one 8-core CCD design and one 16-core CCD design. Perhaps Zen 6 server will stick with merely two CCD designs too, but I have my doubts, after seeing AMD splitting their Zen 5 8-core CCD design into different variants already. I suspect they will make server CPUs with expensive packaging tech at the high end and with less costly packaging tech in the mid or/and lower range — like they have been doing in the Zen 4 generation already — but they may no longer provide for all packaging techniques in a single CCD design, unlike the Zen 4 8-core CCD which had both the conventional IFoP SERDES and the MI300-dedicated TSVs for hybrid bonding onboard and was leaving one of the two dormant.

 

[Markfw]

All I can say about Zen 6 is that most likely the end result(s) will most likely surprise everyone as well as performance expectations.

 

[adroc_thurston]

And why would anybody split mesh to 2 different parts in same silicon?

they didn't?

It's not a mesh - data can't take different path at different mesh points which have obvious advantage at clock speeds - ringbus can operate at core speed where mesh logic can only operate at much lower frequencies

It is a mesh that operates very much at cclk.

And because it's not a mesh but a way to split ring distance to half do not except AMD increase their CCD size over 16 without going to real mesh network scheme

it's a real mesh lol.
Is this qanon for semis nerds or what

 

[naukkis]

it's a real mesh lol.
Is this qanon for semis nerds or what

Mesh network can route packets from source to 3 different location. So doing 16 core mesh would result 4x4 grid or designer would get booted from his job instantly. Ring bus instead is point to point which leads sillicon designs to grow in one direction because it's pretty much only way to do it without leaving center section unused. Ladder optimization on network normally would mean routing source to two possible destinations - but in case of Zen5 2x8 topology doing so would be just pointless - for lowest distance between two stops would always need just one crossing so instead connecting just connecting cores in other sides of ring so packet can be send on closer point of destination would achieve just same effect with plain ringbus point to point routing, which is topology AMD seems to be using.

 

[Joe NYC]

Now we need some proper benchmarks.

Seeing this long bar, imagine the 32c Venice Dense die

It will probably be a square with 2 x 16

 

[adroc_thurston]

Mesh network can route packets from source to 3 different location.

Sort of.

So doing 16 core mesh would result 4x4 grid or designer would get booted from his job instantly.

No?

just same effect with plain ringbus point to point routing, which is topology AMD seems to be using.

Turin-D is a 2*8 mesh.
It's in their ISSCC presentation.

 

[OneEng2]

Turin is Zen 5, Venice is going to be Zen 6.
I presume the Turin-dense die shot only went by mistake into the Zen 6 thread.

Ahh.

I am still betting that the Zen 6 DC dense version (whatever they call it) will have several 32c Zen 6c CCD's ... made on N2 of course.

I am still not convinced that AMD will use N2 for desktop and laptop though. We will see.

 

[Thibsie]

Three CCD Configurations?New IOD? Could we have a beast trio in 2026:Zen 6 with DDR6 with a new AM6 socket?
Speculate at will.

po

 

[Saylick]

Turin is Zen 5, Venice is going to be Zen 6.
I presume the Turin-dense die shot only went by mistake into the Zen 6 thread.

Yeah, I had a brain fart moment there. My mistake.

 

[poke01]

@adroc_thurston , what are your thoughts on fmax with Zen6 DT? After stagnation are we back now that N2 is confirmed?

 

[Hulk]

I think AMD will Keep It Simple with Zen 6. 24 cores and ~10% IPC increase, maybe a few hundred MHz frequency increase under load due to lower power with the new node. Put it all together and you've got a solid bump from Zen 5.

 

[Makaveli]

I think AMD will Keep It Simple with Zen 6. 24 cores and ~10% IPC increase, maybe a few hundred MHz frequency increase under load due to lower power with the new node. Put it all together and you've got a solid bump from Zen 5.

Agreed also hope for faster 1:1 memory speed increase and will probably hit 6Ghz on boost clocks!

12 Core single CCD.

 

[Saylick]

I think AMD will Keep It Simple with Zen 6. 24 cores and ~10% IPC increase, maybe a few hundred MHz frequency increase under load due to lower power with the new node. Put it all together and you've got a solid bump from Zen 5.

Yeah, AMD doesn’t need to go for a moonshot product. Just improve where Zen 5 was weak, i.e. IO die, and make an incremental but logical gain in its strengths.

 

[Josh128]

Please, please, please don't misquote me. My reply was specifically in reference to the question, which was about Cinebench performance.

Now please post some CB scores to show that I was correct with my reply.

Here you go. Whats ARL got? I honestly dont know but Im guessing less than ~350 because I trolled Mr. Biggie Shatz, the biggest Intel shill at WCCFTECH (RIP), with this score multiple times asking what he got with his 285K, and all I got back was deflection and doublespeak. He was proud of his suicide R24 run though.

🤣🤡

 

[adroc_thurston]

what are your thoughts on fmax with Zen6 DT?

It'll be decently higher but idk how much.

24 cores and ~10% IPC increase, maybe a few hundred MHz frequency increase under load due to lower power with the new node

I don't think N2X is, uh, "lower power".

Just improve where Zen 5 was weak,

That would mean tripling the L2 capacity and that's just not happening.

 

[naukkis]

Turin-D is a 2*8 mesh.
It's in their ISSCC presentation.

Where did you find that statement? They did tell that for Zen5 they added ladder optimizations to their ring design which obviously result being able to double ring capacity from 8 to 16. And physical implementation tells that they use that -physical design is to optimize routing distances and with ringbus even with ladders makes it ringular.

 

[adroc_thurston]

Where did you find that statement?

AMD's ISSCC presentation on Zen5.

They did tell that for Zen5 they added ladder optimizations to their ring design which obviously result being able to double ring capacity from 8 to 16. And physical implementation tells that they use that -physical design is to optimize routing distances and with ringbus even with ladders makes it ringular.

this is qanon for tech nerds.
blergh.