Zen APUs made by GloFo, 14nm FinFET node, and packaged by Amkor

[MrTeal]

i know you can use much smaller bumps, but i haven't seen anything says you have to.

You need to, in order to get the density of bumps on the die to use HBM. You also wouldn't be able to mix and match on the same chip, as the standoff height of the different sized bumps would be different.

You likely could get away with mixing and matching chips though. GPU die + HBM could use a high density pitch between them, while the CPU could still use a standard pitch that would allow it to connect to an organic substrate for CPU-only options. At that point though you're essentially building a dGPU on the CPU, which does eliminate many of the advantages of an APU.

 

[Dresdenboy]

YAZT

Yet Another Zen Thread?

 

[itsmydamnation]

You need to, in order to get the density of bumps on the die to use HBM. You also wouldn't be able to mix and match on the same chip, as the standoff height of the different sized bumps would be different.

why does a wider bump have to be taller? How do people switch between organic interposers and none? When you look at Fiji, Tonga and Tahiti the memory interfaces look different but the I/O area all looks very similar.

You likely could get away with mixing and matching chips though. GPU die + HBM could use a high density pitch between them, while the CPU could still use a standard pitch that would allow it to connect to an organic substrate for CPU-only options. At that point though you're essentially building a dGPU on the CPU, which does eliminate many of the advantages of an APU.

Width of interface and throughput and latency of interface are two very different things. its the distance from CPU to dGPU and the switch-fabric nature of PCI-E that makes it's latency higher, putting the CPU and GPU next to each other and having a point to point link running PCI-E phy will dramatically reduce that. Notice how a say PCI-E phy, AMD would run there coherent protocol over the top of that.

 

[DrMrLordX]

Just to add to this raging debate i.e. if it hasn't been posted already http://kotaku.com/sources-sony-is-working-on-a-ps4-5-1765723053

Boo I already posted that.

 

[frozentundra123456]

Do you think it can really do native 4k? Seems like a big jump. Maybe upscaled or 30FPS.

 

[Silverforce11]

Do you think it can really do native 4k? Seems like a big jump. Maybe upscaled or 30FPS.

Fury X class performance can easily do 4K 30 fps. More than that in many games currently running maxed settings. If they dial down settings a notch, it's suddenly ~45 fps.

With added efficiency of HSA on and console API, it will be 4K 60 fps capable. Just don't expect max settings, or poorly optimized features like VXAO on consoles.

Polaris 10 ~232mm2, on the interposer will deliver that along with an updated Zen CPU.

 

[frozentundra123456]

Yea, but that is the point. Are you going to put the performance of a 600 dollar gpu into a console and sell the whole thing for 450.00? Maybe in 2 or 3 years, but I just dont see it for a refresh. I know newer gpus will be more powerful, but I think they will be very expensive, at least initially.

 

[Silverforce11]

Yea, but that is the point. Are you going to put the performance of a 600 dollar gpu into a console and sell the whole thing for 450.00? Maybe in 2 or 3 years, but I just dont see it for a refresh. I know newer gpus will be more powerful, but I think they will be very expensive, at least initially.

It's a node transition, that's the point of it. You bring great perf/w and perf/$ leap. The latter is possible, but obviously depending on how marketing views it.

Polaris 10 at 232mm2 isn't a large chip.

They could easily sell next-gen consoles at $499 to $599 (VR edition!) and gamers will still upgrade to it. Having the latest and greatest is a huge deal for our consumerism society. Add to that the competitive advantage, imagine playing online games at higher resolution and 60 fps vs 30... Sony and MS would be a fool not to capitalize on faster console cycles.

 

[Dresdenboy]

I'm still wondering about the bandwidth between a dGPU box and the main console. Which connection would it use?

 

[frozentundra123456]

It's a node transition, that's the point of it. You bring great perf/w and perf/$ leap. The latter is possible, but obviously depending on how marketing views it.

Polaris 10 at 232mm2 isn't a large chip.

They could easily sell next-gen consoles at $499 to $599 (VR edition!) and gamers will still upgrade to it. Having the latest and greatest is a huge deal for our consumerism society. Add to that the competitive advantage, imagine playing online games at higher resolution and 60 fps vs 30... Sony and MS would be a fool not to capitalize on faster console cycles.

We will see i guess. It *is* just a rumor. I could see it for next gen, but for a mid cycle, I am still skeptical.

 

[cbn]

If you first design something for an interposer, you are going to need it. Both for the CPU or GPU alone. You will need more chip designs. Plus you need interconnects on all chips you wish to use and such. This will also add cost and size.

And yes, 5$ would completely break the lower end. Specially for a company where 50 million $ can mean the difference between loss or a profit.

Remember people buy CPU performance before GPU performance. If the CPU doesn't deliver, the IGP is meaningless as shown by current sales.

Assuming the big iGPU Zen consumer APU "for interposer only" die is designed as 4C/8T that should yield mostly 4C/8T, some 3C/6T and just a very small amount of 2C/4T.

If the interposer allows for a larger BGA interface (which I imagine it would) this should also give AMD more flexibility with power than we see with socket BGA FP4 (which I believe is 45W limit)....possibly 65W or more for the new BGA interposer socket.

So maybe in ideal situations we see 4C/8T and 3C/6T being used in higher end mobile and 2C/4T large iGPU used for BGA desktop/lower end mobile. This with a choice of dual or triple cTDP levels (ie, 35W, 65W or 35W, 65W or 95W).

2C/4T Zen with large iGPU which is the worst case scenario bin (assuming enough TDP) should do well enough in games and other activities.

So then the question becomes is 2C/4T Zen and large iGPU justifiable for a $5 interposer? I would think it seems reasonable enough even for this low/harvested bin. With that mentioned, how much does the actual HBM2 cost? Example: 2 High stack of HBM2 for 2GB at 128GB/s.

 

[AtenRa]

Hell, even porting Kaveri to 14nm LPP would make a better APU than Intels Skylake 2+3e.

https://vimeo.com/142694548

Kaveri at 28nm HPP

Die size = 245mm2
CPU max Clock = 4,1GHz base (A10 7890K)
iGPU clock = 866MHz (A10 7890K)
TDP = 95W (A10-7890K)

Kaveri at 14nm LPP (using high-speed VLT)

Die size = ~70mm2
CPU max Clock = 5GHz ??
iGPU clock = 1100MHz ??
TDP = 35W ??

Now add ZEN CPU cores, Polaris iGPU and HBM 2 and we could have a 120mm2 die at 35w TDP that is faster than the PS4 in a laptop format.
Im sure lots of OEMs would like something like that for $250-300.

They could also make a half die (~70mm2) (2x ZEN CPU cores and 512 Polaris shaders) that would be faster than Skylake Dual Core GT3e easily.
This SKU could easily sell for $200-250 for the Laptop market.

 

[Ancalagon44]

You wouldn't get a TDP less than 50% of the old generation without changing the architecture substantially. And, improvements to TDP will be limited if you try to increase clockspeed at the same time.

 

[AtenRa]

You wouldn't get a TDP less than 50% of the old generation without changing the architecture substantially. And, improvements to TDP will be limited if you try to increase clockspeed at the same time.

ARM Cortex A9 comparison of the iGPU (Falcon neon) on the three nodes.

High-Speed LVT and regular RVT

 

[AtenRa]

Now that im thinking more of the possibilities of the 14nm LPP,

Porting Vishera Quad Module 8 core die to 14nm LPP could have an outcome of a 5GHz 80-90mm2 die at 55W TDP ??

Edit: well Vishera is made at 32nm SOI so it could be somewhat different than 28nm Planar.

 

[R0H1T]

Now that im thinking more of the possibilities of the 14nm LPP,

Porting Vishera Quad Module 8 core die to 14nm LPP could have an outcome of a 5GHz 80-90mm2 die at 55W TDP ??

Edit: well Vishera is made at 32nm SOI so it could be somewhat different than 28nm Planar.

That's a bit optimistic, too optimistic IMO, but 95~110W would likely be possible. Then again clocking anything to 5GHz on a new node would be a feat in itself.

 

[Ancalagon44]

Now that im thinking more of the possibilities of the 14nm LPP,

Porting Vishera Quad Module 8 core die to 14nm LPP could have an outcome of a 5GHz 80-90mm2 die at 55W TDP ??

Edit: well Vishera is made at 32nm SOI so it could be somewhat different than 28nm Planar.

Why on Earth would AMD bother to die shrink such an awful architecture?

There are very good reasons why Zen has so little in common with Bulldozer and its derivatives.

Even Excavator, the newest iteration, is slower than Thuban, clock for clock. In other words, it has lower IPC than Thuban, which is now positively ancient.

 

[coercitiv]

Porting Vishera Quad Module 8 core die to 14nm LPP could have an outcome of a 5GHz 80-90mm2 die at 55W TDP ??

How did you come up with the 55W TDP for a 5Ghz chip?

 

[AtenRa]

Why on Earth would AMD bother to die shrink such an awful architecture?

I was only talking of the possibilities of the 14nm LPP node and what would happen if Vishera was ported to 14nm LPP. Im not saying AMD will port Vishera to 14nm LPP.

 

[ShintaiDK]

I was only talking of the possibilities of the 14nm LPP node and what would happen if Vishera was ported to 14nm LPP. Im not saying AMD will port Vishera to 14nm LPP.

You are not getting a 5Ghz 55W Kaveri APU on 14LPP.

Using your kind of logic we should have 20Ghz CPUs/GPUs now just zipping power. And the next GPUs should run at 2Ghz+ with Polaris 11(120mm2) beating Fury X with 50%.

The hype train never gets old does it?

 

[AtenRa]

How did you come up with the 55W TDP for a 5Ghz chip?

From the tables above.

14nm LPP gives you both an increase in Fmax and a reduction of leakage.

Increasing the Fmax to 5GHz on 14nm LPP vs 4GHz on 32nm SOI (Vishera) would decrease the power by a large margin of 50-60%.

Static power (Idle state) would also decrease substantially.

 

[ShintaiDK]

From the tables above.

14nm LPP gives you both an increase in Fmax and a reduction of leakage.

Increasing the Fmax to 5GHz on 14nm LPP vs 4GHz on 32nm SOI (Vishera) would decrease the power by a large margin of 50-60%.

Static power (Idle state) would also decrease substantially.

And this is where you go terrible wrong. Trying to extrapolate to X random designs.

 

[AtenRa]

You are not getting a 5Ghz 55W Kaveri APU on 14LPP.

According to the tables above, you could increase the Fmax by 2.5x on the 14nm LPP vs 28nm HPP.

5GHz over 4GHz is only 1.25x.

So at 14nm LPP we could have a 4GHz Kaveri at 25-30W TDP

Or

a 5GHz Kaveri at 35-45W TDP.

 

[ShintaiDK]

According to the tables above, you could increase the Fmax by 2.5x on the 14nm LPP vs 28nm HPP.

5GHz over 4GHz is only 1.25x.

So at 14nm LPP we could have a 4GHz Kaveri at 25-30W TDP

Or

a 5GHz Kaveri at 35-45W TDP.

No. Just no. The thermal density also goes up with a factor 7-8x.

 

[AtenRa]

No. Just no. The thermal density also goes up with a factor 7-8x.

??