Zen APUs made by GloFo, 14nm FinFET node, and packaged by Amkor

[Dresdenboy]

Wouldn't an IVR (and HBM for that matter) reduce the number of pins needed?

~350 extra pins doesn't really seem necessary from what we've seen advertised so far. That's just about the right number for another dual channel MC if they want to make the socket extensible in the future, but that seems unlikely.

I think it depends on where that IVR sits. Maybe there is a design, which works more efficiently (and doesn't need Intel's FIVR know how), when given lots of different voltages. Although The Stilt already said, that there won't be more voltage rails.

Two more channels might be worth a thought, as the gap between mem B/W and compute power continues to widen. For an APU with Polaris like GPU efficiency gains and more powerful CPU cores (possibly without that heavy throttling) might either need HBM or more mem channels. HBM likely is a bigger cost factor than some more channels (or at least it moves the costs off package).

 

[krumme]

Fottemberg teases its big at SA and that makes no sence just for some extra ordinary memory lanes. Same goes for extra power.
Come on guys !

 

[Dresdenboy]

Yea i get that, but how many pins do you need for that?

It depends on the design, while moving parts of the whole circuit on or off package.

Havnt Carrizo per IP adaptive voltage?

This still has been marked as "in development" on the Carrizo slides.

Fottemberg teases its big at SA and that makes no sence just for some extra ordinary memory lanes. Same goes for extra power.
Come on guys !

Yeah, being used to 8 channels and 32 cores per socket, who cares about two additional channels. Wait, wasn't there just a discussion about Carrizo being crippled with only one channel? ^^

-> dresdenboy -> krumme

off topic question of the day ; does the PIT(Programmable Interval Timer) still factor into todays x86 designs/concepts or is it called something else? How and where?

- or just ignore at will

Is that an important detail for derivating Zen's performance? Other than the A20 gate this might still be around. But isn't that part of the MB electronics? I'm mostly using RDTSC, RDTSCP.

 

[deasd]

Fottemberg teases its big at SA and that makes no sence just for some extra ordinary memory lanes. Same goes for extra power.
Come on guys !

I bet more pins due to either more than triple-channel memory or HBM.(latter is much more possible)

 

[MrTeal]

I bet more pins due to either more than triple-channel memory or HBM.(latter is much more possible)

HBM wouldn't increase pin count other than possibly another voltage rail. The whole point of it is you have another 1k pins or so per stack, but they all stay on the interposer. They never hit the socket.

 

[The Stilt]

14nm LPP gives you both an increase in Fmax and a reduction of leakage.

Why does everyone assume that smaller transistor size will increase the Fmax, when all available examples beyond 32nm prove the opposite?

-- 32nm SHP SOI -> 28nm (GF28A / GF28HPP)
-- 32nm P1268 HKMG GL -> 22nm P1270 FinFet
-- 22nm P1270 FinFet -> 14nm P1272 FinFet

Also unless you are designing a chipset for a pocket calculator, you can pretty much forget about getting the full (0.25 scale) out of 28nm to 14nm transition. For anything even remotely high performance you'll see something like 0.4 - 0.5 scale in that transition. Until a certain point it is up to the designer to decide how tight the design will be, depending on design targets (area, cost, power optimized at the expence of performance / purely performance).

 

[cbn]

With 14nm using 20nm BEOL that would be a 50% reduction in area compared to 28nm (which uses 28nm BEOL).

That could lead to some pretty good gains in iGPU size.

Someone correct me if I am wrong, but if each GCN 1.x CU (ie, 64sp) uses 7.5mm2 on 28nm that would come out to be 3.75mm2 on 14nm.

 

[krumme]

It depends on the design, while moving parts of the whole circuit on or off package.


This still has been marked as "in development" on the Carrizo slides.


Yeah, being used to 8 channels and 32 cores per socket, who cares about two additional channels. Wait, wasn't there just a discussion about Carrizo being crippled with only one channel? ^^


Is that an important detail for derivating Zen's performance? Other than the A20 gate this might still be around. But isn't that part of the MB electronics? I'm mostly using RDTSC, RDTSCP.

Eg. What parts moved off package?
How do you interprete per ip?
You are right about per ip not in carrizo
Even the per parts still not fully implemented;
http://techreport.com/review/27853/amd-previews-carrizo-apu-offers-insights-into-power-savings/3

 

[ShintaiDK]

With 14nm using 20nm BEOL that would be a 50% reduction in area compared to 28nm (which uses 28nm BEOL).

That could lead to some pretty good gains in iGPU size.

Someone correct me if I am wrong, but if each GCN 1.x CU (ie, 64sp) uses 7.5mm2 on 28nm that would come out to be 3.75mm2 on 14nm.

Even if we assume that. Your 3.75mm2 part cost the same or more as the 7.5mm2 part

So if you want bigger you are going to pay up.

 

[IntelUser2000]

Also unless you are designing a chipset for a pocket calculator, you can pretty much forget about getting the full (0.25 scale) out of 28nm to 14nm transition.

There's a better reason.

The decrease in pitch from 28nm to 14nm doesn't allow that. 0.25 best-case scaling can only happen if pitches Contacted Gate Pitch x Minimum Metal Pitch(M1) both decrease to 0.5x.

It seems that the max scaling from 28nm GF to 16nm TSMC is only about 0.66x.

You have a point about Fmax. The highest ever clocked chip is in the 9GHz range with insanely exotic setups. I don't think a regular chip will *ever* get to that range.

Fottemberg teases its big at SA and that makes no sence just for some extra ordinary memory lanes. Same goes for extra power.
Come on guys !

You don't think a 1600-2000 SP APU with HBM memory would be big news?

 

[ItsAlive]

I don't see why they couldn't just take an R9 Nano, cut the chip in half, and die shrink it. A full sized R9 Nano at 28nm with all the extra power cost of the entire PCB only uses around 200w, so adding just the chip to an apu shouldn't add more than 200w. Cutting the chip in half should drastically reduce the power consumption, and then the die shrink would cut it down even further.

R9 Nano Stock: 200w
R9 chip only -10%: 180w
Cut in half: 100w
Die shrunk: 66w

These are all just basic estimations, please let me know if my numbers are off base. I tried to estimate toward the higher end of the spectrum. They could also lower clocks a bit to lower power consumption, but with a lower power cpu on a new node I really dont think they would have to.

This could allow them to essentially remove the PCI express card slots on a custom motherboard. Integrate wifi to the motherboard, integrate msata SSD, and once HBM2 is available they can use 16GB on chip 8GB for video 8GB for system RAM. They could then delete the ram slots entirely from the motherboard.

Think Pico ITX sized system with quad core and R9 graphics.

 

[IntelUser2000]

These are all just basic estimations, please let me know if my numbers are off base. I tried to estimate toward the higher end of the spectrum. They could also lower clocks a bit to lower power consumption, but with a lower power cpu on a new node I really dont think they would have to.

Things are nowhere that simple.
-Certain circuits like I/O can't be just cut in half, meaning layout changes
-How do you communicate between CPU and GPU?
-Power management between the two is different. For one thing, the GPU has far higher idle power than CPU, and far slower with changes too
-The process used in both may be different. What's the impact of using one process variant?
-Companies exist to earn money. That means they'd want to make derivatives. That means what makes sense on high end makes no sense on low end

Anything that requires layout changes take few years. Before APUs were released AMD has said it takes additional year for their discrete GPU architecture to reach APUs. So that's another insight on whether its that easy to make such changes.

and once HBM2 is available they can use 16GB on chip 8GB for video 8GB for system RAM. They could then delete the ram slots entirely from the motherboard.

HBM is only being used in the highest configurations because they concluded the cost is too high. One stack for 128GB/s bandwidth is fine, but enough to have 16GB capacity? I guess they can price the APU at $600+. It might make sense, but it might not.

 

[PPB]

I don't see why they couldn't just take an R9 Nano, cut the chip in half, and die shrink it. A full sized R9 Nano at 28nm with all the extra power cost of the entire PCB only uses around 200w, so adding just the chip to an apu shouldn't add more than 200w. Cutting the chip in half should drastically reduce the power consumption, and then the die shrink would cut it down even further.

R9 Nano Stock: 200w
R9 chip only -10%: 180w
Cut in half: 100w
Die shrunk: 66w

These are all just basic estimations, please let me know if my numbers are off base. I tried to estimate toward the higher end of the spectrum. They could also lower clocks a bit to lower power consumption, but with a lower power cpu on a new node I really dont think they would have to.

This could allow them to essentially remove the PCI express card slots on a custom motherboard. Integrate wifi to the motherboard, integrate msata SSD, and once HBM2 is available they can use 16GB on chip 8GB for video 8GB for system RAM. They could then delete the ram slots entirely from the motherboard.

Think Pico ITX sized system with quad core and R9 graphics.

Dont need to cut nano (full fiji) in half. There is tonga for that.

More pins in same package size = smaller pitch. Hopefully this doesnt mean filmsier pins. The other day i broke a 478 pentium 4's already bent pin almost by just looking at it, lol. In the other hand I never had bad experiencies handling bent pins on AMx chips.

Max 140w for am4's package is good considering it will also host APUs. 24CU+4c8t zen+HBM = we can only dream.

 

[ItsAlive]

Things are nowhere that simple.
-Certain circuits like I/O can't be just cut in half, meaning layout changes
-How do you communicate between CPU and GPU?
-Power management between the two is different. For one thing, the GPU has far higher idle power than CPU, and far slower with changes too
-The process used in both may be different. What's the impact of using one process variant?
-Companies exist to earn money. That means they'd want to make derivatives. That means what makes sense on high end makes no sense on low end

I get that it wouldn't be as simple as cutting the chip in half, as you said some areas of the chip cant be cut in half, but power would be drastically reduced.

As far as designing the APU and how it communicates with the GPU, wouldn't they already be in the midst of designing this for Zen APUs?

I would expect it to take some time to design of course, but Nano was released in Sept. last year so the tech has been around for awhile.

An extra year of design time would just give them time for the price of HBM2 to come down.

 

[ItsAlive]

Dont need to cut nano (full fiji) in half. There is tonga for that.

More pins in same package size = smaller pitch. Hopefully this doesnt mean filmsier pins. The other day i broke a 478 pentium 4's already bent pin almost by just looking at it, lol. In the other hand I never had bad experiencies handling bent pins on AMx chips.

Max 140w for am4's package is good considering it will also host APUs. 24CU+4c8t zen+HBM = we can only dream.

The only reason I said Nano (Fiji) is because it is already designed to work with HBM. I realize it will be an entirely new chip.

 

[cbn]

With 14nm using 20nm BEOL that would be a 50% reduction in area compared to 28nm (which uses 28nm BEOL).

That could lead to some pretty good gains in iGPU size.

Someone correct me if I am wrong, but if each GCN 1.x CU (ie, 64sp) uses 7.5mm2 on 28nm that would come out to be 3.75mm2 on 14nm.

Even if we assume that. Your 3.75mm2 part cost the same or more as the 7.5mm2 part

So if you want bigger you are going to pay up.

Since these consumer APUs are designed for laptop first I'm thinking the bigger problem will probably be power.....and iGPU size will have to be constrained because of that.

However, if Polaris does in fact scale 2.5x Performance per watt compared to 28nm GCN 1.x that means a 35W/42W AC boost laptop would have the equivalent of 1280sp 28nm GCN 1.x @ 750 Mhz (with the CPU cores simultaneously throttling). (re: Carrizo @ 512sp gets around 750Mhz at 35W/42W AC boost during CPU intensive gameplay).

Assuming that marketing number of "2.5x performance per watt" is really 2x performance per watt that still net the equivalent of 1024sp 28nm GCN 1.x @ 750 Mhz (with the CPU cores simultaneously throttling).

Looking at the performance per watt of Vega (below) it looks like AMD is claiming 3.5x to 4x compared to 28nm GCN 1.x GPUs, so based the 35W/42W performance of Carrizo 512sp @ 750 Mhz that would equate to somewhere around 1792sp 28nm GCN 1.x @ 750Mhz to 2048sp 28nm GCN 1.x @ 750Mhz (with the CPU cores simultaneously throttling) for a Zen/Vega 35W/42W APU. Assuming the true performance per watt is 3x that would come out to 1536sp 28nm GCN 1.x @ 750Mhz (with the CPU cores simultaneously throttling) for a Zen/Vega 35W/42W APU.

P.S. As far as the final power rating the Zen laptop APU goes, I'm thinking it probably be 45W (just like the Skylake GT4e)....mainly because of the CPU cores.

 

[cbn]

Remember these FirePro APUs:

http://www.amd.com/en-us/products/graphics/workstation/firepro-3d/apu#

I do wonder if we will see a Zen laptop firepro APU as well?

 

[IntelUser2000]

I get that it wouldn't be as simple as cutting the chip in half, as you said some areas of the chip cant be cut in half, but power would be drastically reduced.

It's *much* more complicated than that.

Ahh, regardless AMD engineers and management knows far more than either of us, or even probably everyone on AT Forums. They may screw up, but they are working on a very complicated project.

 

[Headfoot]

Well, we heard the same expectations when Kaveri came out around the time of the consoles. A projected 1024 shader part with GDDR5 that was going to take over the gaming market. We all know how that turned out.

Is this a joke? A 1152 shader GDDR5 part did take over the gaming market. It's called the PS4 and it sold millions of units. Most AAA gaming is done on consoles though PC gaming is by no means dead or dying.

 

[frozentundra123456]

Is this a joke? A 1152 shader GDDR5 part did take over the gaming market. It's called the PS4 and it sold millions of units. Most AAA gaming is done on consoles though PC gaming is by no means dead or dying.

Yea I am laughing hysterically inside. What I meant to say, and thought was clear, since this is the PC cpu section, not the Console Gaming section, was the rumors for a super APU for the PC with GDDR5.

 

[Headfoot]

Yea I am laughing hysterically inside. What I meant to say, and thought was clear, since this is the PC cpu section, not the Console Gaming section, was the rumors for a super APU for the PC with GDDR5.

'Gaming market' is subject to a lot of interpretations. Some include phones because of the astonishing amount of revenue there, some include facebook browser games for the same reason. I assumed the 'gaming market' was AAA gaming, which is done on consoles and gaming PCs, since the other markets are not performance sensitive, so hardware doesn't matter much. If you want to narrow the field of comparison to APUs, then the PS4 pulls even farther away from its competition since Gaming PCs using discrete graphics are the largest competitor to the consoles.

 

[frozentundra123456]

So are you denying that there were rumors of a 1024 shader, APU for the PC using GDDR5?

 

[Headfoot]

What? I have no idea. Who cares?

 

[frozentundra123456]

What? I have no idea. Who cares?

If you have no idea and "don't care", why did you make such a rude reply to my post?

 

[Dresdenboy]

So are you denying that there were rumors of a 1024 shader, APU for the PC using GDDR5?

There is also a 16 CU Bristol Ridge rumour, while the BenchLife slides show 12 CUs for BR (incl. CPU cores).

IIRC, AMD tech docs mentioned GDDR5 capability of the IMC. And there is also a 256b FPU bit (still 0).