Zen hasn't taped out yet

[Dresdenboy]

This plan sounds like a fast death sentence for AMD ,in other words, BD no 2. Why go with many small cores plus SMT when you can have similar MT performance but better ST performance If you go with a moderate amount of wider cores+SMT?

"Small" is just about the absolute area. IPC will be different though.

 

[Arachnotronic]

So just a hypothetical example:

-Broadwell-E performs 10-20% better than Zen
-Zen costs $600
-Broadwell-E costs $1000

Which one would you pick?

What a ridiculous argument. 8 core Broadwell-E will probably slot nicely into the $600 price point, so it's not an "either or" between your two scenarios.

I get that you really want AMD to succeed, but you shouldn't assume that the people determining which SKUs to offer at Intel at complete morons.

 

[Dresdenboy]

- Im with you there 100% but that part about ST performance not being that important. I think ST performance will still be the number one metric 10 years from now.

Integer ST performance should be fine with Zen. Just ST FP stuff might not see a big jump from XV.

 

[Abwx]

Integer ST performance should be fine with Zen. Just ST FP stuff might not see a big jump from XV.

ST FP perf should get a much bigger uplift than 40%, Zen FPU is a beefed Flex FPU and this latter has comparable throughput than a HW core, and a Zen core should have comparable FP throughput than an XV module.

 

[The Stilt]

If it has higher than 40% uplift over Excavator, why didn´t AMD say so. It´s not like they can afford to make any understatements...

 

[Fjodor2001]

What a ridiculous argument. 8 core Broadwell-E will probably slot nicely into the $600 price point, so it's not an "either or" between your two scenarios.

It was just an example, don't get stuck on exact prices.

The point is this: Assuming 8 core Broadwell-E is 10-20% faster than Zen, how much more will you be willing to spend to get that extra performance?

I think for a lot of people when the difference starts to get as small as 10-20% and they can save a couple of $100, they'll opt for Zen. Lately AMD has been much more behind Intel performance wise than that, so AMD has not really been an option for them even if AMD was cheaper. But with Zen, I think AMD can get close enough performance-wise to be a realistic option again for a lot of people.

 

[AtenRa]

Zen might be a bit weak on the FP side, but if the small core hypothesis is correct, AMD might throw lots of cores on a die. SMT, core renaming (for power management), IVR, high integer throughput, and the promised cache subsystem should give nice performance there. It would be able to stay at higher average clocks with all cores+SMT active, as a small core footprint doesn't cause that much static power consumption (while active), making efficient use of available TDP. Size comparison: ~4-5 mm² (incl. L2) vs. 8 mm² Skylake.

L4 HBM2 cache + NVM (managed as one huge address space) seems likely and might help to be competitive.

Big Data might be bottlenecked by the 2 AGUs or cache misses, whatever comes first, as it has 70 mem operands per 100 instructions.

What's not so safe to assume yet (but found in patents and papers): stack cache (for power efficiency), uOp cache, checkpointing (low branch misprediction latency), SMT thread prioritization (not that useful for servers), near threshold computing, reliable computing, redundant computing, asynchronous logic.

So, back to Llano ??? 2x Llano cores were almost the same as a single SandyBridge. But this time "Llano" has 40% increase of IPC and SMT.

Could they make such a wide core with 4x ALUs, 2x AGUs and FPU unit at 4-5mm2 on the 14nm FF ???

And if ZEN core is only 4-5mm2 they could make a 8x Core 16x Threads die at 120-140mm2 or even smaller (depending on the L3 cache size and hyper-transports or equivalent).

 

[Abwx]

If it has higher than 40% uplift over Excavator, why didn´t AMD say so. It´s not like they can afford to make any understatements...

Because those 40% are an average including Integer code wich does not need as much uplift to be on par with Intel.

A Zen core FPU is more powerfull than the one in an XV module, so with its four ALUs a Zen core should have in SMT at least the same throughput than an XV module.

For instance an XV module at 3GHz score 1.575 in CB 11.5, without the CMT penalty it would score 1.762, so this range is about what should be expected from Zen in a 1C/2T configuration, the proportion brought by SMT in those scores is of course an unknown.

 

[mrmt]

s

Zen might be a bit weak on the FP side, but if the small core hypothesis is correct, AMD might throw lots of cores on a die. SMT, core renaming (for power management), IVR, high integer throughput, and the promised cache subsystem should give nice performance there. It would be able to stay at higher average clocks with all cores+SMT active, as a small core footprint doesn't cause that much static power consumption (while active), making efficient use of available TDP. Size comparison: ~4-5 mm² (incl. L2) vs. 8 mm² Skylake.

So do you think AMD could cram enough hardware on 4.5mm^2 to be competitive in terms of performance and efficiency against a 8mm^2 Skylake core on integer performance, meaning that Intel is basically doubling the size of the core just to get better FP performance?

 

[The Stilt]

Because those 40% are an average including Integer code wich does not need as much uplift to be on par with Intel.

A Zen core FPU is more powerfull than the one in an XV module, so with its four ALUs a Zen core should have in SMT at least the same throughput than an XV module.

For instance an XV module at 3GHz score 1.575 in CB 11.5, without the CMT penalty it would score 1.762, so this range is about what should be expected from Zen in a 1C/2T configuration, the proportion brought by SMT in those scores is of course an unknown.

Single Excavator CU running at 3.0GHz scores 1.54 in Cinebench R11.5. Two native cores (CMT core disabled from each unit) enabled it scores 1.68 (91.6% CMT yield).

If we expect AMD to match Intel in SMT yield (~26.5% in Cinebench), then the native Zen core would score 1.328 at 3.0GHz. That would be 58% improvement in IPC for this type of workloads. Not impossible, but I think the SMT yield matching Intel´s 26.5% is a slightly tall order especially for their first SMT design.

 

[Abwx]

Single Excavator CU running at 3.0GHz scores 1.54 in Cinebench R11.5. Two native cores (CMT core disabled from each unit) enabled it scores 1.68 (91.6% CMT yield).

If we expect AMD to match Intel in SMT yield (~26.5% in Cinebench), then the native Zen core would score 1.328 at 3.0GHz. That would be 58% improvement in IPC for this type of workloads. Not impossible, but I think the SMT yield matching Intel´s 26.5% is a slightly tall order especially for their first SMT design.

A 4C/8T Zen wouldnt make sense if it couldnt match a 8C/8T XV in throughput/GHz given that the latter would be likely more efficient at equal node, although at the expense of ST IPC...

As for CB scores/GHz :

http://www.planet3dnow.de/cms/18564...er-architekturen/subpage-rendering-cinebench/

 

[itsmydamnation]

s

So do you think AMD could cram enough hardware on 4.5mm^2 to be competitive in terms of performance and efficiency against a 8mm^2 Skylake core on integer performance, meaning that Intel is basically doubling the size of the core just to get better FP performance?

im sure Intel optimises the hell out of it, but in the "real world" tm anything above 64 bit data paths is trading max perfomance on complex code for throughput. You could see this both from a core size and power perspective. The QUESTION is how big of a tax is Intel 256 bit vs amd 128bit.

Most enterprise and consumer apps dont even use simd and 256bit simd is an even smaller subset of that.

 

[The Stilt]

A 4C/8T Zen wouldnt make sense if it couldnt match a 8C/8T XV in throughput/GHz given that the latter would be likely more efficient at equal node, although at the expense of ST IPC...

As for CB scores/GHz :

http://www.planet3dnow.de/cms/18564...er-architekturen/subpage-rendering-cinebench/

The Cinebench numbers I gave you are based on actual measurements (I do have the reference FX-8800P system), not on extrapolated figures.

 

[mrmt]

im sure Intel optimises the hell out of it, but in the "real world" tm anything above 64 bit data paths is trading max perfomance on complex code for throughput. You could see this both from a core size and power perspective. The QUESTION is how big of a tax is Intel 256 bit vs amd 128bit.

Most enterprise and consumer apps dont even use simd and 256bit simd is an even smaller subset of that.

Considering that Intel 14nm is better than Samsung 14nm that would have to be above 100%. Do you think it is remotely close to this number?

 

[Abwx]

The Cinebench numbers I gave you are based on actual measurements (I do have the reference FX-8800P system), not on extrapolated figures.

I know that you have a plateform but your score is one among many others, as for extrapolating scores this is a moot argument as CB 11.5 scale perfectly with frequency, and eventual scaling error is way lower than the bench variability at a given frequency.

Indeed your score is below the one that i linked and wich is 1.05pts/GHz/4C with a penalty at 0.8936, higher than with Kaveri, ST and MT in respect of this latter being improved by 11.9% and 9% respectively.

Considering that Intel 14nm is better than Samsung 14nm that would have to be above 100%. Do you think it is remotely close to this number?

Lol, yet another random and blanket statement by some specialist of the physics of semiconductors..

GF s 14nm LPP LVT is 20% more efficient than Intel s 14nm, the 14nm LPP sLVT will bury it by another 10% in dynamic power comsumption, Intel better work their process than relying on bullish marketers...

 

[cytg111]

Considering that Intel 14nm is better than Samsung 14nm...

I like your analytical thinking on this. Also, do you think my father can beat your father?

 

[Arachnotronic]

GF s 14nm LPP LVT is 20% more efficient than Intel s 14nm, the 14nm LPP sLVT will bury it by another 10% in dynamic power comsumption, Intel better work their process than relying on bullish marketers...

Proof?

 

[cytg111]

Proof?

Proof its not?

 

[The Stilt]

GF s 14nm LPP LVT is 20% more efficient than Intel s 14nm, the 14nm LPP sLVT will bury it by another 10% in dynamic power comsumption, Intel better work their process than relying on bullish marketers...

P1272 or P1273?
AFAIK Intel hasn´t revealed any in-depth technical data about their processes, or do you have some available?

 

[Arachnotronic]

Proof its not?

LOL, proof that a Flying Spaghetti Monster doesn't exist?

If you claim something, the burden of proof is upon the person who made the claim.

 

[DrMrLordX]

If it has higher than 40% uplift over Excavator, why didn´t AMD say so. It´s not like they can afford to make any understatements...

AMD sort of undershot on XV's improvement over SR on those benches you ran for me on OCN. The only bench that showed 5% improvement was Cinebench R10. The other three were 11%, 11%, and 22%. Those last three were all SIMD-heavy fp workloads fwiw.

Single Excavator CU running at 3.0GHz scores 1.54 in Cinebench R11.5. Two native cores (CMT core disabled from each unit) enabled it scores 1.68 (91.6% CMT yield).

If we expect AMD to match Intel in SMT yield (~26.5% in Cinebench), then the native Zen core would score 1.328 at 3.0GHz. That would be 58% improvement in IPC for this type of workloads. Not impossible, but I think the SMT yield matching Intel´s 26.5% is a slightly tall order especially for their first SMT design.

If Zen runs like that, we're in for some serious pain. That will not be a fast chip.

 

[cytg111]

LOL, proof that a Flying Spaghetti Monster doesn't exist?

If you claim something, the burden of proof is upon the person who made the claim.

My proof :
http://www.usatoday.com/story/news/...etti-monster-massachusetts-religion/75862946/

Now yours

 

[frozentundra123456]

Looks quite normal compared to some of the outlandish crap posted in these forums.

 

[pm]

P1272 or P1273?
AFAIK Intel hasn´t revealed any in-depth technical data about their processes, or do you have some available?

I'm not sure that I want to jump into the war over who has the best process technology - the term "best" is already a subjective definition...

But, if you want data to make a semi-informed decision, then the best place to look is the IEDM (International Electron Devices Meeting) conference papers.

For example this paper by Intel on it's 14nm process:
http://www.intel.com/content/dam/ww...foundry/intel-14nm-iedm-2014-presentation.pdf

Depending on your level of technical paper access, you can get similar papers for TSMC and IBM and, not so much GF and Samsung.

 

[Abwx]

Proof?

Proof i already posted it, with due calculations and explanations that could be understood by a 16 year old college student who wouldnt had deserted his maths courses..

P1272 or P1273?
AFAIK Intel hasn´t revealed any in-depth technical data about their processes, or do you have some available?

Dont know what thoses numbers are related to but i m talking of the process used to fab both BDW and SKL CPUs, compared to GF s 14nm LPP LVT.

At 2.4GHz the latter necessitate 1.1x lower voltage than the former, just this parameter say that the perf/Watt advantage ratio is automaticaly 1.1^2 for whom did bother to check some basic transistors rules.

When voltage must be increased by 10% to reach a given frequency it could mean two things separetaly or a combination of both.

First is the most likely and is that Intel s transistors have 1.21x lower (trans)conductance than GF s, this can be straightfowardly compensated with a voltage higher by a ratio wich is the root square of the missing conductance ratio, this is a direct consequence of a fundamental property of mosfet/fet transistors wich are device whose output/input caracteristic is a square law.

Second is that Intel s transistors and circuit layout has globaly 1.21x higher parasistic capacitance, wich is unlikely given that the geometries design rules are the same for everybody and that there s no reason that Intel engineers whould had screwed this indeed better mastered design phase.