The Zeppelin die currently the only die using the Zen processor. Ryzen 3/5/7 contains one Zeppelin die, Ryzen Threadripper contains two, and EPYC contains four. Here is what I have been able to piece together about the I/O capabilities of the chip:
The Zeppelin die supports 32 PCIe lanes, in two groups of 16.
It is not clear to what extent these groups can be subdivided. One group can be subdivided into at least 8/8. The ability to subdivide this group is disabled on Ryzen 3/5/7 unless the processor detects an X370 chip set.
The second group can, I hypothesize, be divided into 4/2/2/2/2/1/1/1/1.
In addition to supporting the PCI protocol, one of these groups of 16 (it's not clear which one) can support the Infinity Fabric protocol as well as PCI. (The Infinity Fabric protocol presumably looks like PCIe at a low level, but uses messages optimized for managing memory.) This support is disabled on processors other than the two socket EPYC models.
The die also contains four USB controllers supporting speeds up to 10 Gbps. Since 10 Gbps is faster than the 8 Gpbs supported by a single PCIe lane, I hypothesize that each controllers is connected two PCIe links from the second group. These controllers are unconditionally enabled on Ryzen 3/5/7, meaning that the 8 PCIe links feeding them are not available for other purposes. They are disabled on Ryzen Threadripper and EPYC.
The die also contains two SATA controllers. These each take one PCIe lane from the second group. These can be optionally enabled on Ryzen 3/5/7, and are disabled on Ryzen Threadripper and EPYC. If these are disabled, the two PCIe lanes which would feed them are available for other purposes.
Corrections and additional information are welcome.
The Zeppelin die supports 32 PCIe lanes, in two groups of 16.
It is not clear to what extent these groups can be subdivided. One group can be subdivided into at least 8/8. The ability to subdivide this group is disabled on Ryzen 3/5/7 unless the processor detects an X370 chip set.
The second group can, I hypothesize, be divided into 4/2/2/2/2/1/1/1/1.
In addition to supporting the PCI protocol, one of these groups of 16 (it's not clear which one) can support the Infinity Fabric protocol as well as PCI. (The Infinity Fabric protocol presumably looks like PCIe at a low level, but uses messages optimized for managing memory.) This support is disabled on processors other than the two socket EPYC models.
The die also contains four USB controllers supporting speeds up to 10 Gbps. Since 10 Gbps is faster than the 8 Gpbs supported by a single PCIe lane, I hypothesize that each controllers is connected two PCIe links from the second group. These controllers are unconditionally enabled on Ryzen 3/5/7, meaning that the 8 PCIe links feeding them are not available for other purposes. They are disabled on Ryzen Threadripper and EPYC.
The die also contains two SATA controllers. These each take one PCIe lane from the second group. These can be optionally enabled on Ryzen 3/5/7, and are disabled on Ryzen Threadripper and EPYC. If these are disabled, the two PCIe lanes which would feed them are available for other purposes.
Corrections and additional information are welcome.